公开(公告)号：US20230420331A1

公开(公告)日：2023-12-28

申请号：US17809039

申请日：2022-06-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ban-Li Wu ,  Tsung-Hsien Chiang ,  Tzu-Sung Huang ,  Chao-Hsien Huang ,  Chia-Lun Chang ,  Hsiu-Jen Lin ,  Ming Hung Tseng ,  Hao-Yi Tsai

IPC分类号： H01L23/367 ,  H01L25/16 ,  H01L23/498 ,  H01L21/48 ,  H01L23/373

CPC分类号： H01L23/3677 ,  H01L25/16 ,  H01L23/49822 ,  H01L23/49833 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/3735 ,  H01L23/49838 ,  H01L24/16

摘要： A semiconductor package including one or more heat dissipation systems and a method of forming are provided. The semiconductor package may include one or more integrated circuit dies, an encapsulant surrounding the one or more integrated circuit dies, a redistribution structure over the one or more integrated circuit dies and the encapsulant. The redistribution structure may include one or more heat dissipation systems, which are electrically isolated from remaining portions of the redistribution structure. Each heat dissipation system may include a first metal pad, a second metal pad, and one or more metal vias connecting the first metal pad to the second metal pad.

公开(公告)号：US11244906B2

公开(公告)日：2022-02-08

申请号：US16881002

申请日：2020-05-22

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tzu-Sung Huang ,  Cheng-Chieh Hsieh ,  Hsiu-Jen Lin ,  Hui-Jung Tsai ,  Hung-Yi Kuo ,  Hao-Yi Tsai ,  Ming-Hung Tseng ,  Yen-Liang Lin ,  Chun-Ti Lu ,  Chung-Ming Weng

IPC分类号： H01L23/538 ,  H01L23/31 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00

摘要： A package structure including a first semiconductor die, a second semiconductor die, first conductive pillars and a first insulating encapsulation is provided. The first semiconductor die includes a semiconductor substrate, an interconnect structure and a first redistribution circuit structure. The semiconductor substrate includes a first portion and a second portion disposed on the first portion. The interconnect structure is disposed on the second portion, the first redistribution circuit structure is disposed on the interconnect structure, and the lateral dimension of the first portion is greater than the lateral dimension of the second portion. The second semiconductor die is disposed on the first semiconductor die. The first conductive pillars are disposed on the first redistribution circuit structure of the first semiconductor die. The first insulating encapsulation is disposed on the first portion. The first insulating encapsulation laterally encapsulates the second semiconductor die, the first conductive pillars and the second portion.

公开(公告)号：US20240312692A1

公开(公告)日：2024-09-19

申请号：US18674351

申请日：2024-05-24

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tzu-Sung Huang ,  Chen-Hua Yu ,  Hao-Yi Tsai ,  Hung-Yi Kuo ,  Ming Hung Tseng

IPC分类号： H01F27/28 ,  H01F17/00 ,  H01F38/14 ,  H01F41/04 ,  H01F41/10 ,  H02J50/10 ,  H02J50/80

CPC分类号： H01F27/2804 ,  H01F38/14 ,  H01F41/041 ,  H01F41/10 ,  H01L28/10 ,  H02J50/10 ,  H02J50/80 ,  H01F2017/0086

摘要： Coil structures and methods of forming are provided. The coil structure includes a substrate. A plurality of coils is disposed over the substrate, each coil comprising a conductive element that forms a continuous spiral having a hexagonal shape in a plan view of the coil structure. The plurality of coils is arranged in a honeycomb pattern, and each conductive element is electrically connected to an external electrical circuit.

公开(公告)号：US11133269B2

公开(公告)日：2021-09-28

申请号：US16655247

申请日：2019-10-17

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chun-Ti Lu ,  Hao-Yi Tsai ,  Ming-Hung Tseng ,  Tsung-Hsien Chiang ,  Yen-Liang Lin ,  Tzu-Sung Huang

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L25/10

摘要： A semiconductor package and a manufacturing method for the semiconductor package are provided. The package comprises a die, through interlayer vias (TIVs), a dielectric film, a backside film and solder paste portions. The TIVs are disposed beside the semiconductor die and a molding compound laterally surrounds the die and the TIVs. The dielectric film is disposed on a backside of the semiconductor die, and the backside film is disposed on the dielectric film. The backside film has at least one of a coefficient of thermal expansion (CTE) and a Young's modulus larger than that of the dielectric film. The solder paste portions are disposed on the TIVs and located within openings penetrating through the dielectric film and the backside film. There is a recess located at an interface between the dielectric film and the backside film within the opening.

公开(公告)号：US20210225723A1

公开(公告)日：2021-07-22

申请号：US17201856

申请日：2021-03-15

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tzu-Sung Huang ,  Ming Hung Tseng ,  Yen-Liang Lin ,  Hao-Yi Tsai ,  Chi-Ming Tsai ,  Chung-Shi Liu ,  Chih-Wei Lin ,  Ming-Che Ho

IPC分类号： H01L23/31 ,  H01L23/16 ,  H01L23/522 ,  H01L21/768 ,  H01L21/56 ,  H01L23/528

摘要： In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.

公开(公告)号：US20230245939A1

公开(公告)日：2023-08-03

申请号：US18297927

申请日：2023-04-10

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tzu-Sung Huang ,  Ming Hung Tseng ,  Yen-Liang Lin ,  Hao-Yi Tsai ,  Chi-Ming Tsai ,  Chung-Shi Liu ,  Chih-Wei Lin ,  Ming-Che Ho

IPC分类号： H01L23/31 ,  H01L23/16 ,  H01L23/522 ,  H01L21/768 ,  H01L21/56 ,  H01L23/528

CPC分类号： H01L23/3157 ,  H01L23/16 ,  H01L23/5226 ,  H01L21/76843 ,  H01L21/56 ,  H01L21/76802 ,  H01L23/528

摘要： In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.

公开(公告)号：US20210358870A1

公开(公告)日：2021-11-18

申请号：US17385222

申请日：2021-07-26

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tzu-Sung Huang ,  Chen-Hua Yu ,  Hung-Yi Kuo ,  Hao-Yi Tsai ,  Ming Hung Tseng

IPC分类号： H01L23/64 ,  H01L21/48 ,  H01L21/56 ,  H01L23/485 ,  H01L23/552 ,  H01L49/02 ,  H01L21/683

摘要： In an embodiment, a device includes: a conductive shield on a first dielectric layer; a second dielectric layer on the first dielectric layer and the conductive shield, the first and second dielectric layers surrounding the conductive shield, the second dielectric layer including: a first portion disposed along an outer periphery of the conductive shield; a second portion extending through a center region of the conductive shield; and a third portion extending through a channel region of the conductive shield, the third portion connecting the first portion to the second portion; a coil on the second dielectric layer, the coil disposed over the conductive shield; an integrated circuit die on the second dielectric layer, the integrated circuit die disposed outside of the coil; and an encapsulant surrounding the coil and the integrated circuit die, top surfaces of the encapsulant, the integrated circuit die, and the coil being level.

公开(公告)号：US20210118811A1

公开(公告)日：2021-04-22

申请号：US16655247

申请日：2019-10-17

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chun-Ti Lu ,  Hao-Yi Tsai ,  Ming-Hung Tseng ,  Tsung-Hsien Chiang ,  Yen-Liang Lin ,  Tzu-Sung Huang

IPC分类号： H01L23/00 ,  H01L25/10 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

摘要： A semiconductor package and a manufacturing method for the semiconductor package are provided. The package comprises a die, through interlayer vias (TIVs), a dielectric film, a backside film and solder paste portions. The TIVs are disposed beside the semiconductor die and a molding compound laterally surrounds the die and the TIVs. The dielectric film is disposed on a backside of the semiconductor die, and the backside film is disposed on the dielectric film. The backside film has at least one of a coefficient of thermal expansion (CTE) and a Young's modulus larger than that of the dielectric film. The solder paste portions are disposed on the TIVs and located within openings penetrating through the dielectric film and the backside film. There is a recess located at an interface between the dielectric film and the backside film within the opening.

公开(公告)号：US20230154764A1

公开(公告)日：2023-05-18

申请号：US17655645

申请日：2022-03-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tzu-Sung Huang ,  Tsung-Hsien Chiang ,  Ming Hung Tseng ,  Hao-Yi Tsai ,  Yu-Hsiang Hu ,  Chih-Wei Lin ,  Lipu Kris Chuang ,  Wei Lun Tsai ,  Kai-Ming Chiang ,  Ching Yao Lin ,  Chao-Wei Li ,  Ching-Hua Hsieh

IPC分类号： H01L21/48 ,  H01L23/498

CPC分类号： H01L21/4857 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/32

摘要： A method includes forming a first metal mesh over a carrier, forming a first dielectric layer over the first metal mesh, and forming a second metal mesh over the first dielectric layer. The first metal mesh and the second metal mesh are staggered. The method further includes forming a second dielectric layer over the second metal mesh, attaching a device die over the second dielectric layer, with the device die overlapping the first metal mesh and the second metal mesh, encapsulating the device die in an encapsulant, and forming redistribution lines over and electrically connecting to the device die.

公开(公告)号：US11626339B2

公开(公告)日：2023-04-11

申请号：US17201856

申请日：2021-03-15

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tzu-Sung Huang ,  Ming Hung Tseng ,  Yen-Liang Lin ,  Hao-Yi Tsai ,  Chi-Ming Tsai ,  Chung-Shi Liu ,  Chih-Wei Lin ,  Ming-Che Ho

IPC分类号： H01L23/31 ,  H01L23/16 ,  H01L23/522 ,  H01L21/768 ,  H01L21/56 ,  H01L23/528

摘要： In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.