公开(公告)号：US20240112924A1

公开(公告)日：2024-04-04

申请号：US18150256

申请日：2023-01-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsu-Hsien Chen ,  Chen-Shien Chen ,  Ting Hao Kuo ,  Chi-Yen Lin ,  Yu-Chih Huang

IPC: H01L21/56 ,  H01L21/306 ,  H01L21/768 ,  H01L21/78 ,  H01L23/522 ,  H01L23/538

CPC classification number: H01L21/563 ,  H01L21/30604 ,  H01L21/76802 ,  H01L21/78 ,  H01L23/5226 ,  H01L23/5389

Abstract: An integrated circuit package including integrated circuit dies with slanted sidewalls and a method of forming are provided. The integrated circuit package may include a first integrated circuit die, a first gap-fill dielectric layer around the first integrated circuit die, a second integrated circuit die underneath the first integrated circuit die, and a second gap-fill dielectric layer around the second integrated circuit die. The first integrated circuit die may include a first substrate, wherein a first angle is between a first sidewall of the first substrate and a bottom surface of the first substrate, and a first interconnect structure on the bottom surface of the first substrate, wherein a second angle is between a first sidewall of the first interconnect structure and the bottom surface of the first substrate. The first angle may be larger than the second angle.

公开(公告)号：US11011501B2

公开(公告)日：2021-05-18

申请号：US16103921

申请日：2018-08-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hsuan Tai ,  Hao-Yi Tsai ,  Yu-Chih Huang ,  Chia-Hung Liu ,  Ting-Ting Kuo ,  Ban-Li Wu ,  Ying-Cheng Tseng ,  Chi-Hui Lai

IPC: H01L23/498 ,  H01L25/10 ,  H01L23/31 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00

Abstract: A package structure including a first redistribution layer, a semiconductor die, through insulator vias, an insulating encapsulant and a second redistribution layer. The first redistribution layer includes a dielectric layer, a conductive layer, and connecting portions electrically connected to the conductive layer. The dielectric layer has first and second surfaces, the connecting portions has a first side, a second side, and sidewalls joining the first side to the second side. The first side of the connecting portions is exposed from and coplanar with the first surface of the dielectric layer. The semiconductor die is disposed on the second surface of the dielectric layer. The through insulator vias are connected to the conductive layer. The insulating encapsulant is disposed on the dielectric layer and encapsulating the semiconductor die and the through insulator vias. The second redistribution layer is disposed on the semiconductor die and over the insulating encapsulant.

公开(公告)号：US20210074694A1

公开(公告)日：2021-03-11

申请号：US17099179

申请日：2020-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chih Huang ,  Chi-Hui Lai ,  Ban-Li Wu ,  Ying-Cheng Tseng ,  Ting-Ting Kuo ,  Chih-Hsuan Tai ,  Hao-Yi Tsai ,  Chuei-Tang Wang ,  Chung-Shi Liu ,  Chen-Hua Yu ,  Chiahung Liu

IPC: H01L25/16 ,  H01L23/498 ,  H01L21/48 ,  H01L21/50 ,  H01L23/31 ,  H01L25/10 ,  H01L23/00

Abstract: A semiconductor package includes an integrated passive device (IPD) including one or more passive devices over a first substrate; and metallization layers over and electrically coupled to the one or more passive devices, where a topmost metallization layer of the metallization layers includes a first plurality of conductive patterns; and a second plurality of conductive patterns interleaved with the first plurality of conductive patterns. The IPD also includes a first under bump metallization (UBM) structure over the topmost metallization layer, where the first UBM structure includes a first plurality of conductive strips, each of the first plurality of conductive strips electrically coupled to a respective one of the first plurality of conductive patterns; and a second plurality of conductive strips interleaved with the first plurality of conductive strips, each of the second plurality of conductive strips electrically coupled to a respective one of the second plurality of conductive patterns.

公开(公告)号：US20190139886A1

公开(公告)日：2019-05-09

申请号：US15877398

申请日：2018-01-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yu Chen ,  Chih-Hua Chen ,  Ching-Hua Hsieh ,  Hsiu-Jen Lin ,  Yu-Chih Huang ,  Yu-Peng Tsai ,  Chia-Shen Cheng ,  Chih-Chiang Tsao ,  Jen-Jui Yu

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L23/522

Abstract: A package structure includes an insulating encapsulation, at least one die, and conductive structures. The at least one die is encapsulated in the insulating encapsulation. The conductive structures are located aside of the at least one die and surrounded by the insulating encapsulation, and at least one of the conductive structures is electrically connected to the at least one die. Each of the conductive structures has a first surface, a second surface opposite to the first surface and a slant sidewall connecting the first surface and the second surface, and each of the conductive structures has a top diameter greater than a bottom diameter thereof, and wherein each of the conductive structures has a plurality of pores distributed therein.

公开(公告)号：US12113022B2

公开(公告)日：2024-10-08

申请号：US16884035

申请日：2020-05-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Cheng Tseng ,  Hao-Yi Tsai ,  Yu-Chih Huang ,  Chia-Hung Liu

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/16 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L23/5383 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/24 ,  H01L25/167 ,  H01L23/3121 ,  H01L25/0652 ,  H01L2224/24011 ,  H01L2224/24146 ,  H01L2225/06548

Abstract: A semiconductor package includes a lower encapsulated semiconductor device, a lower redistribution structure, an upper encapsulated semiconductor device, and an upper redistribution structure. The lower redistribution structure is disposed over and electrically connected to the lower encapsulated semiconductor device. The upper encapsulated semiconductor device is disposed over the lower encapsulated semiconductor device and includes a sensor die having a pad and a sensing region, an upper encapsulating material at least laterally encapsulating the sensor die, and an upper conductive via extending through the upper encapsulating material and connected to the lower redistribution structure. The upper redistribution structure is disposed over the upper encapsulated semiconductor device. The upper redistribution structure covers the pad of the sensor die and has an opening located on the sensing region of the sensor die.

公开(公告)号：US11842993B2

公开(公告)日：2023-12-12

申请号：US18064690

申请日：2022-12-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Cheng Tseng ,  Yu-Chih Huang ,  Chih-Hsuan Tai ,  Ting-Ting Kuo ,  Chi-Hui Lai ,  Ban-Li Wu ,  Chiahung Liu ,  Hao-Yi Tsai

IPC: H01L27/01 ,  H01L21/70 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  H01L49/02 ,  H01L25/10

CPC classification number: H01L27/013 ,  H01L21/705 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5286 ,  H01L24/13 ,  H01L28/10 ,  H01L28/20 ,  H01L28/40 ,  H01L25/105 ,  H01L2224/13025 ,  H01L2225/1035 ,  H01L2225/1058

Abstract: A semiconductor device includes passive electrical components in a substrate; and an interconnect structure over the passive electrical components, conductive features of the interconnect structure being electrically coupled to the passive electrical components. The conductive features of the interconnect structure includes a first conductive line over the substrate; a conductive bump over the first conductive line, where in a plan view, the conductive bumps has a first elongated shape and is entirely disposed within boundaries of the first conductive line; and a first via between the first conductive line and the conductive bump, the first via electrically connected to the first conductive line and the conductive bump, where in the plan view, the first via has a second elongated shape and is entirely disposed within boundaries of the conductive bump.

公开(公告)号：US20230253384A1

公开(公告)日：2023-08-10

申请号：US18301555

申请日：2023-04-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chih Huang ,  Chi-Hui Lai ,  Ban-Li Wu ,  Ying-Cheng Tseng ,  Ting-Ting Kuo ,  Chih-Hsuan Tai ,  Hao-Yi Tsai ,  Chuei-Tang Wang ,  Chung-Shi Liu ,  Chen-Hua Yu ,  Chiahung Liu

IPC: H01L25/16 ,  H01L23/498 ,  H01L21/48 ,  H01L21/50 ,  H01L23/31 ,  H01L25/10 ,  H01L23/00

CPC classification number: H01L25/162 ,  H01L21/50 ,  H01L21/4857 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/20 ,  H01L25/16 ,  H01L25/105 ,  H01G4/00 ,  H01L24/08 ,  H01L24/16 ,  H01L2224/08225 ,  H01L2224/16235 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/15313 ,  H01L2924/19011 ,  H01L2924/19105

Abstract: A semiconductor package includes an integrated passive device (IPD) including one or more passive devices over a first substrate; and metallization layers over and electrically coupled to the one or more passive devices, where a topmost metallization layer of the metallization layers includes a first plurality of conductive patterns; and a second plurality of conductive patterns interleaved with the first plurality of conductive patterns. The IPD also includes a first under bump metallization (UBM) structure over the topmost metallization layer, where the first UBM structure includes a first plurality of conductive strips, each of the first plurality of conductive strips electrically coupled to a respective one of the first plurality of conductive patterns; and a second plurality of conductive strips interleaved with the first plurality of conductive strips, each of the second plurality of conductive strips electrically coupled to a respective one of the second plurality of conductive patterns.

公开(公告)号：US11631658B2

公开(公告)日：2023-04-18

申请号：US17099179

申请日：2020-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chih Huang ,  Chi-Hui Lai ,  Ban-Li Wu ,  Ying-Cheng Tseng ,  Ting-Ting Kuo ,  Chih-Hsuan Tai ,  Hao-Yi Tsai ,  Chuei-Tang Wang ,  Chung-Shi Liu ,  Chen-Hua Yu ,  Chiahung Liu

IPC: H01L25/16 ,  H01L23/498 ,  H01L21/48 ,  H01L21/50 ,  H01L23/31 ,  H01L25/10 ,  H01L23/00 ,  H01G4/00 ,  H01L25/065

Abstract: A semiconductor package includes an integrated passive device (IPD) including one or more passive devices over a first substrate; and metallization layers over and electrically coupled to the one or more passive devices, where a topmost metallization layer of the metallization layers includes a first plurality of conductive patterns; and a second plurality of conductive patterns interleaved with the first plurality of conductive patterns. The IPD also includes a first under bump metallization (UBM) structure over the topmost metallization layer, where the first UBM structure includes a first plurality of conductive strips, each of the first plurality of conductive strips electrically coupled to a respective one of the first plurality of conductive patterns; and a second plurality of conductive strips interleaved with the first plurality of conductive strips, each of the second plurality of conductive strips electrically coupled to a respective one of the second plurality of conductive patterns.

公开(公告)号：US20230110420A1

公开(公告)日：2023-04-13

申请号：US18064690

申请日：2022-12-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Cheng Tseng ,  Yu-Chih Huang ,  Chih-Hsuan Tai ,  Ting-Ting Kuo ,  Chi-Hui Lai ,  Ban-Li Wu ,  Chiahung Liu ,  Hao-Yi Tsai

IPC: H01L27/01 ,  H01L23/528 ,  H01L23/00 ,  H01L21/768 ,  H01L21/70 ,  H01L23/522

Abstract: A semiconductor device includes passive electrical components in a substrate; and an interconnect structure over the passive electrical components, conductive features of the interconnect structure being electrically coupled to the passive electrical components. The conductive features of the interconnect structure includes a first conductive line over the substrate; a conductive bump over the first conductive line, where in a plan view, the conductive bumps has a first elongated shape and is entirely disposed within boundaries of the first conductive line; and a first via between the first conductive line and the conductive bump, the first via electrically connected to the first conductive line and the conductive bump, where in the plan view, the first via has a second elongated shape and is entirely disposed within boundaries of the conductive bump.

公开(公告)号：US11309225B2

公开(公告)日：2022-04-19

申请号：US16714801

申请日：2019-12-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hsuan Tai ,  Chih-Hua Chen ,  Hao-Yi Tsai ,  Yu-Chih Huang ,  Chia-Hung Liu ,  Ting-Ting Kuo

IPC: H01L23/31 ,  H01L21/66 ,  H01L21/56 ,  H01L23/532 ,  H01L23/00 ,  H01L23/522 ,  H01L21/78 ,  H01L25/10 ,  H01L21/683 ,  H01L25/00 ,  H01L23/538 ,  H01L25/065

Abstract: A package structure and a method of manufacturing the same are provided. The package structure includes a die, a redistribution layer (RDL) structure, a through integrated fan-out via (TIV) and a conductive terminal. The RDL structure is disposed on and electrically connected to the die. The TIV is laterally aside the die and extends to contact a bottom surface and a sidewall of a redistribution layer of the RDL structure. The conductive terminal is electrically connected to the die through the RDL structure and the TIV.