公开(公告)号：US20240387392A1

公开(公告)日：2024-11-21

申请号：US18786873

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Hui-Jung Tsai ,  Hung-Jui Kuo ,  Chung-Shi Liu ,  Han-Ping Pu ,  Ting-Chu Ko

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31

Abstract: In accordance with some embodiments a via is formed over a semiconductor device, wherein the semiconductor device is encapsulated within an encapsulant 129. A metallization layer and a second via are formed over and in electrical connection with the first via, and the metallization layer and the second via are formed using the same seed layer. Embodiments include fully landed vias, partially landed vias in contact with the seed layer, and partially landed vias not in contact with the seed layer.

公开(公告)号：US11569562B2

公开(公告)日：2023-01-31

申请号：US16997958

申请日：2020-08-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ping Wang ,  Chun-Lin Lu ,  Han-Ping Pu ,  Kai-Chiang Wu ,  Chung-Yi Hsu

IPC: H01Q1/22 ,  H01Q9/04 ,  H01L23/31 ,  H01L23/66

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes: patch antennas, encapsulated by a first encapsulant; a device die, vertically spaced apart from the patch antennas, and electrically coupled to the patch antennas; and at least one redistribution structure, disposed between the patch antennas and the device die, and including electromagnetic bandgap (EBG) structures laterally surrounding each of the patch antennas.

公开(公告)号：US11145595B2

公开(公告)日：2021-10-12

申请号：US16706805

申请日：2019-12-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Lin Lu ,  Han-Ping Pu ,  Kai-Chiang Wu ,  Nan-Chin Chuang

IPC: H01L23/52 ,  H01L23/522 ,  H01L23/498 ,  H01L23/528 ,  H01L23/00

Abstract: An integrated fan-out (InFO) package includes a first redistribution structure, a die, an encapsulant, a plurality of first through interlayer vias (TIV), a second redistribution structure, an insulating layer, a supporting layer, and a plurality of conductive patches. The die is disposed on the first redistribution structure. The encapsulant encapsulates the die. The first TIVs are embedded in the encapsulant. The second redistribution structure is disposed on the die, the first TIVs, and the encapsulant. The first redistribution structure is electrically connected to the second redistribution structure through the first TIVs. The insulating layer is disposed on the first redistribution structure opposite to the die and includes a plurality of air gaps. The supporting layer is over the insulating layer. The conductive patches are over the supporting layer. Locations of the conductive patches correspond to locations of the air gaps of the insulating layer.

公开(公告)号：US20210098385A1

公开(公告)日：2021-04-01

申请号：US17122616

申请日：2020-12-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Ping Pu ,  Hsiao-Wen Lee

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/683 ,  H01L21/768

Abstract: The present disclosure provides a packaged device that includes a first dielectric layer; a second dielectric layer, formed over the first dielectric layer, that includes a device substrate and a via extending from the first dielectric layer and through the second dielectric layer; and a third dielectric layer, formed over the second dielectric layer, that includes a conductive pillar extending through the third dielectric layer, wherein the conductive pillar is electrically coupled to the via of the second dielectric layer.

公开(公告)号：US20200343203A1

公开(公告)日：2020-10-29

申请号：US16924116

申请日：2020-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Chiang Wu ,  Han-Ping Pu ,  Yen-Ping Wang

IPC: H01L23/66 ,  H01L23/498 ,  H01L23/544 ,  H01L21/56 ,  H01L23/31

Abstract: A package structure includes a chip package and an antenna package. The chip package includes at least one semiconductor die and a first insulating encapsulation encapsulating the at least one semiconductor die. The antenna package is located on and electrically coupled to the chip package. The antenna package includes metallic patterns embedded in a second insulating encapsulation, wherein each of the metallic patterns has a first surface, a second surface opposite to the first surface and a side surface connecting the first surface and the second surface, wherein the first surface and the side surface of each of the metallic patterns are covered by the second insulating encapsulation, and the second surface is levelled and coplanar with a third surface of the second insulating encapsulation. A method of manufacturing a package structure is also provided.

公开(公告)号：US20200273773A1

公开(公告)日：2020-08-27

申请号：US16283852

申请日：2019-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Albert Wan ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Chao-Wen Shih ,  Han-Ping Pu ,  Hsin-Yu Pan ,  Sen-Kuei Hsu

IPC: H01L23/373 ,  H01L23/31 ,  H01L23/538 ,  H01L23/66 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01Q1/22 ,  H01Q1/02

Abstract: A semiconductor device including a chip package and an antenna package disposed on the chip package is provided. The chip package includes a semiconductor chip, an encapsulation enclosing the semiconductor chip, and a redistribution structure disposed on the semiconductor chip and the encapsulation and electrically coupled to the semiconductor chip. The antenna package includes an antenna pattern electrically coupled to the chip package, and an intermediate structure disposed between the antenna pattern and the chip package, wherein the intermediate structure comprises a ceramic element in contact with the redistribution structure and thermally dissipating a heat generated from the semiconductor chip.

公开(公告)号：US20200035625A1

公开(公告)日：2020-01-30

申请号：US16421497

申请日：2019-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chuei-Tang Wang ,  Chung-Hao Tsai ,  Chen-Hua Yu ,  Chun-Lin Lu ,  Han-Ping Pu ,  Kai-Chiang Wu

IPC: H01L23/66 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L23/552 ,  H01L21/56 ,  H01L21/48

Abstract: A package includes a semiconductor package including a semiconductor die and a first insulating encapsulation, a substrate, and a second insulating encapsulation. The first insulating encapsulation encapsulates the semiconductor die. The substrate includes a redistribution circuitry, wherein the substrate is electrically coupled to the semiconductor package through the redistribution circuitry. The second insulating encapsulation is disposed on and partially covers the substrate, wherein the substrate is sandwiched between the semiconductor package and the second insulating encapsulation.

公开(公告)号：US20200020628A1

公开(公告)日：2020-01-16

申请号：US16035723

申请日：2018-07-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Yu Huang ,  Han-Ping Pu ,  Ming-Kai Liu ,  Ting-Chu Ko ,  Yung-Ping Chiang ,  Chang-Wen Huang ,  Yu-Sheng Hsieh

IPC: H01L23/522 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538 ,  H01L21/768 ,  H01L23/532 ,  H01L23/00

Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes two dies, an encapsulant, a first metal line and a plurality of dummy vias. The encapsulant is disposed between the two dies. The first metal line is disposed over the two dies and the encapsulant, and electrically connected to the two dies. The plurality of dummy vias is disposed over the encapsulant and aside the first metal line.

公开(公告)号：US12165985B2

公开(公告)日：2024-12-10

申请号：US17818625

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Hui-Jung Tsai ,  Hung-Jui Kuo ,  Chung-Shi Liu ,  Han-Ping Pu ,  Ting-Chu Ko

IPC: H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538

Abstract: In accordance with some embodiments a via is formed over a semiconductor device, wherein the semiconductor device is encapsulated within an encapsulant 129. A metallization layer and a second via are formed over and in electrical connection with the first via, and the metallization layer and the second via are formed using the same seed layer. Embodiments include fully landed vias, partially landed vias in contact with the seed layer, and partially landed vias not in contact with the seed layer.

公开(公告)号：US11894299B2

公开(公告)日：2024-02-06

申请号：US17188787

申请日：2021-03-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Wen Shih ,  Chen-Hua Yu ,  Han-Ping Pu ,  Hsin-Yu Pan ,  Hao-Yi Tsai ,  Sen-Kuei Hsu

IPC: H01L23/52 ,  H01L23/525 ,  H01L23/552 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532 ,  H01L23/29 ,  H01L23/31 ,  H01L21/56 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L23/525 ,  H01L21/56 ,  H01L23/293 ,  H01L23/3192 ,  H01L23/5225 ,  H01L23/5329 ,  H01L23/552 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/14 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76885 ,  H01L23/5286 ,  H01L24/13 ,  H01L2224/0348 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/11622 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/16104 ,  H01L2224/03462 ,  H01L2924/00014

Abstract: A method includes forming a dielectric layer over a contact pad of a device, forming a first polymer layer over the dielectric layer, forming a first conductive line and a first portion of a second conductive line over the first polymer layer, patterning a photoresist to form an opening over the first portion of the second conductive feature, wherein after patterning the photoresist the first conductive line remains covered by photoresist, forming a second portion of the second conductive line in the opening, wherein the second portion of the second conductive line physically contacts the first portion of the second conductive line, and forming a second polymer layer extending completely over the first conductive line and the second portion of the second conductive line.