公开(公告)号：US12062622B2

公开(公告)日：2024-08-13

申请号：US17883568

申请日：2022-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Ping Pu ,  Hsiao-Wen Lee

IPC: H01L23/538 ,  H01L21/683 ,  H01L21/768 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/5389 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76895 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5386 ,  H01L2221/68359 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13024 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/211 ,  H01L2224/214 ,  H01L2224/215 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29166 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/01029 ,  H01L2924/06 ,  H01L2924/0665 ,  H01L2924/07025

Abstract: The present disclosure provides a packaged device that includes a first dielectric layer; a second dielectric layer, formed over the first dielectric layer, that includes a device substrate and a via extending from the first dielectric layer and through the second dielectric layer; and a third dielectric layer, formed over the second dielectric layer, that includes a conductive pillar extending through the third dielectric layer, wherein the conductive pillar is electrically coupled to the via of the second dielectric layer.

公开(公告)号：US11056445B2

公开(公告)日：2021-07-06

申请号：US16731517

申请日：2019-12-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsiao-Wen Lee ,  Hsien-Wen Liu ,  Shin-Puu Jeng

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L21/304 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L21/02 ,  H01L21/48 ,  H01L23/498

Abstract: Package structures are provided. A package structure includes an adhesive layer and a semiconductor substrate over the adhesive layer. The package structure also includes a connector over the semiconductor substrate. The package structure further includes a first buffer layer surrounding the connector. In addition, the package structure includes an encapsulation layer surrounding the first buffer layer. The first buffer layer is sandwiched between the encapsulation layer and the semiconductor substrate, and a sidewall of the encapsulation layer is in direct contact with a sidewall of the first buffer layer and a sidewall of the adhesive layer. The package structure also includes a redistribution layer over the first buffer layer and the encapsulation layer.

公开(公告)号：US20190131273A1

公开(公告)日：2019-05-02

申请号：US15795276

申请日：2017-10-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shuo-Mao Chen ,  Feng-Cheng Hsu ,  Han-Hsiang Huang ,  Hsien-Wen Liu ,  Shin-Puu Jeng ,  Hsiao-Wen Lee

IPC: H01L25/065 ,  H01L25/16 ,  H01L23/538 ,  H01L21/56 ,  H01L25/00

Abstract: Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.

公开(公告)号：US10269720B2

公开(公告)日：2019-04-23

申请号：US15360739

申请日：2016-11-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Ping Pu ,  Hsiao-Wen Lee

IPC: H01L23/02 ,  H01L23/538 ,  H01L23/00 ,  H01L21/768 ,  H01L21/683 ,  H01L23/31 ,  H01L21/56 ,  H01L23/498

Abstract: The present disclosure provides a packaged device that includes a first dielectric layer; a second dielectric layer, formed over the first dielectric layer, that includes a device substrate and a via extending from the first dielectric layer and through the second dielectric layer; and a third dielectric layer, formed over the second dielectric layer, that includes a conductive pillar extending through the third dielectric layer, wherein the conductive pillar is electrically coupled to the via of the second dielectric layer.

公开(公告)号：US20180026067A1

公开(公告)日：2018-01-25

申请号：US15216815

申请日：2016-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiao-Wen Lee ,  Kazuaki Hashimoto ,  Kuo-Chung Yee

IPC: H01L27/146 ,  H01L23/00

CPC classification number: H01L27/14634 ,  H01L24/02 ,  H01L24/13 ,  H01L24/14 ,  H01L24/19 ,  H01L25/50 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/1469 ,  H01L2224/02379 ,  H01L2224/13024 ,  H01L2224/14135 ,  H01L2924/1433 ,  H01L2924/1436

Abstract: A complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) package is provided. The image sensor package comprises a first integrated circuit (IC) die, a second IC die, and a fan-out structure. The first IC die comprises a pixel sensor array, and the second IC die is under and bonded to the first IC die. Further, the fan-out structure is under and bonded to the second IC die. The fan-out structure comprises a third IC die, a fan-out dielectric layer laterally adjacent to the third IC die, a through insulator via (TIV) extending through the fan-out dielectric layer, and one or more redistribution layers (RDLs) under the third IC die and the TIV. The one or more RDLs electrically couple to the third IC die and the TIV. A method for manufacturing the CIS package is also provided.

公开(公告)号：US20210098385A1

公开(公告)日：2021-04-01

申请号：US17122616

申请日：2020-12-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Ping Pu ,  Hsiao-Wen Lee

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/683 ,  H01L21/768

Abstract: The present disclosure provides a packaged device that includes a first dielectric layer; a second dielectric layer, formed over the first dielectric layer, that includes a device substrate and a via extending from the first dielectric layer and through the second dielectric layer; and a third dielectric layer, formed over the second dielectric layer, that includes a conductive pillar extending through the third dielectric layer, wherein the conductive pillar is electrically coupled to the via of the second dielectric layer.

公开(公告)号：US11189596B2

公开(公告)日：2021-11-30

申请号：US16928003

申请日：2020-07-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shuo-Mao Chen ,  Feng-Cheng Hsu ,  Han-Hsiang Huang ,  Hsien-Wen Liu ,  Shin-Puu Jeng ,  Hsiao-Wen Lee

IPC: H01L25/065 ,  H01L25/16 ,  H01L23/538 ,  H01L25/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31

Abstract: Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.

公开(公告)号：US20200343220A1

公开(公告)日：2020-10-29

申请号：US16928003

申请日：2020-07-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shuo-Mao Chen ,  Feng-Cheng Hsu ,  Han-Hsiang Huang ,  Hsien-Wen Liu ,  Shin-Puu Jeng ,  Hsiao-Wen Lee

IPC: H01L25/065 ,  H01L25/16 ,  H01L23/538 ,  H01L25/00 ,  H01L21/56 ,  H01L21/683

Abstract: Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.

公开(公告)号：US11437327B2

公开(公告)日：2022-09-06

申请号：US17122616

申请日：2020-12-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Ping Pu ,  Hsiao-Wen Lee

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/683 ,  H01L21/768 ,  H01L23/31 ,  H01L21/56 ,  H01L23/498

Abstract: The present disclosure provides a packaged device that includes a first dielectric layer; a second dielectric layer, formed over the first dielectric layer, that includes a device substrate and a via extending from the first dielectric layer and through the second dielectric layer; and a third dielectric layer, formed over the second dielectric layer, that includes a conductive pillar extending through the third dielectric layer, wherein the conductive pillar is electrically coupled to the via of the second dielectric layer.

公开(公告)号：US10763239B2

公开(公告)日：2020-09-01

申请号：US15795276

申请日：2017-10-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shuo-Mao Chen ,  Feng-Cheng Hsu ,  Han-Hsiang Huang ,  Hsien-Wen Liu ,  Shin-Puu Jeng ,  Hsiao-Wen Lee

IPC: H01L25/065 ,  H01L25/16 ,  H01L23/538 ,  H01L21/56 ,  H01L25/00 ,  H01L21/683 ,  H01L23/31

Abstract: Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.