公开(公告)号：US20250105173A1

公开(公告)日：2025-03-27

申请号：US18405929

申请日：2024-01-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Meng-Sheng Chang ,  Chia-En Huang ,  Yih Wang

IPC: H01L23/00 ,  G11C17/16 ,  G11C17/18 ,  H10B20/25

Abstract: A memory device includes an array having a plurality of one-time-programmable (OTP) memory cells formed over a side of a substrate, a plurality of word lines (WLs), a plurality of bit lines (BLs), and a plurality of control gate (CG) lines. Each of the OTP memory cells includes a first fuse resistor, a second fuse resistor, a first transistor, and a second transistor. The first and the second fuse resistors are connected to a corresponding one of the BLs, while the first and the second transistors are respectively gated by a first one and a second one of the CG lines. The first transistor, the second transistor, the first fuse resistor, and the second fuse resistor are respectively formed in a first one, a second one, a third one, and a fourth one of a plurality of metallization layers disposed on the side of the substrate.

公开(公告)号：US12249390B2

公开(公告)日：2025-03-11

申请号：US18316743

申请日：2023-05-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chieh Lee ,  Yi-Ching Liu ,  Chia-En Huang ,  Jen-Yuan Chang ,  Yih Wang

IPC: G11C5/06 ,  G11C5/02 ,  H01L23/48 ,  H10B12/00 ,  H10B61/00 ,  H10B63/00 ,  H10N50/01 ,  H10N50/80 ,  H10N70/00

Abstract: A memory device includes a first layer, wherein the first layer includes a first memory array, a first row decoder circuit, and a first column sensing circuit. The memory device includes a second layer disposed with respect to the first layer in a vertical direction. The second layer includes a first peripheral circuit operatively coupled to the first memory array, the first row decoder circuit, and the first column sensing circuit. The memory device includes a plurality of interconnect structures extending along the vertical direction. At least a first one of the plurality of interconnect structures operatively couples the second layer to the first layer.

公开(公告)号：US20250078907A1

公开(公告)日：2025-03-06

申请号：US18460155

申请日：2023-09-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chi Lo ,  Chia-En Huang ,  Yi-Ching Liu ,  Hiroki Noguchi ,  Yih Wang

IPC: G11C11/4091 ,  G11C11/408

Abstract: An integrated circuit includes a sense amplifier connected to a bit line and a bit line bar, a first memory cell configured to store a data signal and selectively output the data signal on at least one of the bit line and the bit line bar in response to a word line signal, a first circuit connected between a first voltage terminal configured to receive a first external voltage and the bit line and having a first enable terminal configured to receive a first enable signal, wherein the first external voltage is different than the data signal, and a second circuit connected between a second voltage terminal configured to receive a second external voltage and the bit line bar and having a second enable terminal configured to receive a second enable signal, wherein the second external voltage is different than the data signal and the first external voltage.

公开(公告)号：US12243589B2

公开(公告)日：2025-03-04

申请号：US17898733

申请日：2022-08-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Pei-Chun Liao ,  Yu-Kai Chang ,  Yi-Ching Liu ,  Yu-Ming Lin ,  Yih Wang ,  Chieh Lee

IPC: G11C16/26 ,  G11C16/08 ,  G11C16/32

Abstract: A memory device is provided, including a memory array, a driver circuit, and recover circuit. The memory array includes multiple memory cells. Each memory cell is coupled to a control line, a data line, and a source line and, during a normal operation, is configured to receive first and second voltage signals. The driver circuit is configured to output at least one of the first voltage signal or the second voltage signal to the memory cells. The recover circuit is configured to output, during a recover operation, a third voltage signal, through the driver circuit to at least one of the memory cells. The third voltage signal is configured to have a first voltage level that is higher than a highest level of the first voltage signal or the second voltage signal, or lower than a lowest level of the first voltage signal or the second voltage signal.

公开(公告)号：US12205648B2

公开(公告)日：2025-01-21

申请号：US17461278

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Meng-Sheng Chang ,  Chia-En Huang ,  Yi-Ching Liu ,  Yih Wang

IPC: G11C7/22 ,  G11C16/04 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/34

Abstract: Disclosed herein are related to a memory array including one-time programmable (OTP) cells. In one aspect, the memory array includes a set of OTP cells including a first subset of OTP cells connected between a first program control line and a first read control line. Each OTP cell of the first subset of OTP cells may include a programmable storage device and a switch connected between the first program control line and the first read control line. The first program control line may extend towards a first side of the memory array along a first direction, and the first read control line may extend towards a second side of the memory array facing away from the first side of the memory array.

公开(公告)号：US12193204B2

公开(公告)日：2025-01-07

申请号：US18157461

申请日：2023-01-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Meng-Sheng Chang ,  Chia-En Huang ,  Yi-Hsun Chiu ,  Yih Wang

IPC: H10B10/00 ,  G11C11/40 ,  G11C11/412 ,  H01L29/06 ,  H01L29/08

Abstract: A memory cell is disclosed. The memory cell includes a first transistor. The first transistor includes a first conduction channel collectively constituted by one or more first nanostructures spaced apart from one another along a vertical direction. The memory cell includes a second transistor electrically coupled to the first transistor in series. The second transistor includes a second conduction channel collectively constituted by one or more second nanostructures spaced apart from one another along the vertical direction. At least one of the one or more first nanostructures is applied with first stress by a first metal structure extending, along the vertical direction, into a first drain/source region of the first transistor.

公开(公告)号：US20240389313A1

公开(公告)日：2024-11-21

申请号：US18789212

申请日：2024-07-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Meng-Sheng Chang ,  Chia-En Huang ,  Yih Wang

IPC: H10B20/20 ,  H01L21/02 ,  H01L27/088 ,  H01L29/04 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: A method for fabricating a semiconductor device includes: forming a fin-based structure protruding from a top boundary of a substrate; forming a first nanosheet-based structure protruding from the top boundary of the substrate; epitaxially growing a first, a second, and a third source/drain (S/D) regions, the first S/D region disposed between the fin-based structure and the first nanosheet-based structure, the second S/D region disposed opposite the fin-based structure from the first S/D region, and the third S/D region disposed opposite the first nanosheet-based structure from the first S/D region, and the first to the third S/D regions having a same conductive type; forming a second nanosheet-based structure protruding from the boundary of the substrate and laterally spaced apart from the first nanosheet-based structure; and epitaxially growing a fourth S/D region disposed opposite the second nanosheet-based structure from the third S/D region.

公开(公告)号：US12094558B2

公开(公告)日：2024-09-17

申请号：US18318264

申请日：2023-05-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Perng-Fei Yuh ,  Meng-Sheng Chang ,  Tung-Cheng Chang ,  Yih Wang

IPC: G11C11/00 ,  G11C5/14 ,  G11C7/10 ,  G11C17/16 ,  G11C17/18

CPC classification number: G11C5/147 ,  G11C7/1084 ,  G11C17/165 ,  G11C17/18

Abstract: One aspect of this description relates to a memory array. The memory array includes a plurality of N-stack pass gates, a plurality of enable lines, a plurality of NMOS stacks, a plurality of word lines, and a matrix of resistive elements. Each N-stack pass gate includes a stage-1 PMOS core device and a stage-N PMOS core device in series. Each stage-1 PMOS is coupled to a voltage supply. Each enable line drives a stack pass gate. Each N-stack selector includes a plurality of NMOS stacks. Each NMOS stack includes a stage-1 NMOS core device and a stage-N NMOS core device in series. Each stage-1 NMOS core device is coupled to a ground rail. Each word line is driving a stack selector. Each resistive element is coupled between a stack pass gate and a stack selector. Each voltage supply is greater than a breakdown voltage for each of the core devices.

公开(公告)号：US20240296887A1

公开(公告)日：2024-09-05

申请号：US18662806

申请日：2024-05-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Perng-Fei Yuh ,  Yih Wang ,  Ku-Feng Lin ,  Jui-Che Tsai ,  Hiroki Noguchi ,  Fu-An Wu

IPC: G11C14/00 ,  G11C11/16 ,  G11C11/419

CPC classification number: G11C14/0081 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/419

Abstract: Disclosed herein is an integrated circuit including multiple magnetic tunneling junction (MTJ) cells coupled to a static random access memory (SRAM). In one aspect, the integrated circuit includes a SRAM having a first port and a second port, and a set of pass transistors coupled to the first port of the SRAM. In one aspect, the integrated circuit includes a set of MTJ cells, where each of the set of MTJ cells is coupled between a select line and a corresponding one of the set of pass transistors.

公开(公告)号：US12075614B2

公开(公告)日：2024-08-27

申请号：US17473678

申请日：2021-09-13

Applicant: Taiwan Semiconductor Manufacturing Company Ltd.

Inventor： Meng-Sheng Chang ,  Chia-En Huang ,  Yih Wang

IPC: H10B20/20 ,  H01L23/525 ,  H10B20/25

CPC classification number: H10B20/20 ,  H01L23/5256 ,  H10B20/25

Abstract: A memory device is disclosed. The memory device includes a substrate having a first side and a second side that is opposite to the first side, and a transistor disposed on the first side of the substrate. The memory device includes a capacitor electrically connected to the transistor and including a first terminal, a second terminal, and an insulation layer interposed between the first and second terminals, at least the insulation layer disposed on the second side of the substrate. The transistor and the capacitor form a one-time programmable (OTP) memory cell.