公开(公告)号：US20150155258A1

公开(公告)日：2015-06-04

申请号：US14616078

申请日：2015-02-06

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chien-Feng Chan ,  Mu-Hsuan Chan ,  Chun-Tang Lin ,  Yi-Che Lai

IPC: H01L23/00 ,  H01L21/56

CPC classification number: H01L24/81 ,  H01L21/441 ,  H01L21/56 ,  H01L23/145 ,  H01L23/147 ,  H01L23/488 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/05572 ,  H01L2224/13022 ,  H01L2224/13084 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81805 ,  H01L2224/81815 ,  H01L2224/81986 ,  H01L2224/83104 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/9211 ,  H01L2224/92125 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/01047 ,  H01L2924/01029

Abstract: A conductive bump structure used to be formed on a substrate having a plurality of bonding pads. The conductive bump structure includes a first metal layer formed on the bonding pads, a second metal layer formed on the first metal layer, and a third metal layer formed on the second metal layer. The second metal layer has a second melting point higher than a third melting point of the third metal layer. Therefore, a thermal compression bonding process is allowed to be performed to the third metal layer first so as to bond the substrate to another substrate, and then a reflow process can be performed to melt the second metal layer and the third metal layer into each other so as to form an alloy portion, thus avoiding cracking of the substrate.

Abstract translation: 用于形成在具有多个接合焊盘的基板上的导电凸块结构。 导电凸块结构包括在接合焊盘上形成的第一金属层，形成在第一金属层上的第二金属层和形成在第二金属层上的第三金属层。 第二金属层的第二熔点高于第三金属层的第三熔点。 因此，首先对第三金属层进行热压接，从而将基板粘合到另一基板上，然后进行回流处理，使第二金属层和第三金属层彼此熔融 从而形成合金部分，从而避免基板的开裂。

公开(公告)号：US20140127838A1

公开(公告)日：2014-05-08

申请号：US13845698

申请日：2013-03-18

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Pin-Cheng Huang ,  Chun-Tang Lin ,  Wen-Tsung Tseng ,  Yi-Che Lai

IPC: H01L21/66

CPC classification number: H01L22/14 ,  H01L21/6836 ,  H01L22/20 ,  H01L23/147 ,  H01L23/367 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0655 ,  H01L2221/68331 ,  H01L2221/68381 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2224/83005 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/16195 ,  H01L2924/351 ,  H01L2924/37001 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/81

Abstract: A method of testing a semiconductor package is provided, including: disposing at least an interposer on a top surface of an adhesive layer, the interposer having a first surface and a second surface opposite to the first surface, a plurality of conductive elements disposed between the second surface of the interposer and the adhesive layer; disposing at least a semiconductor chip on the first surface of the interposer, and performing an electrical test on the semiconductor chip via the conductive elements, wherein if there are a plurality of semiconductor chips that are disposed on the first surface of the interposer, the step of disposing the semiconductor chip and performing the electrical test on the semiconductor chip is iterated; and removing the adhesive layer. By using the method, the fabrication cost and equipment cost of the semiconductor package are reduced, and product yield is increased.

Abstract translation: 提供了一种测试半导体封装的方法，包括：至少在粘合剂层的顶表面上设置插入件，所述插入件具有第一表面和与第一表面相对的第二表面，多个导电元件设置在第二表面之间 插入器的第二表面和粘合剂层; 在所述插入件的第一表面上设置至少一个半导体芯片，并且经由所述导电元件对所述半导体芯片进行电测试，其中如果存在设置在所述插入件的第一表面上的多个半导体芯片，则所述步骤 重复设置半导体芯片并对半导体芯片进行电气测试; 并去除粘合剂层。 通过使用该方法，半导体封装的制造成本和设备成本降低，产品产量增加。

公开(公告)号：US20170229387A1

公开(公告)日：2017-08-10

申请号：US15434599

申请日：2017-02-16

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Wen-Tsung Tseng ,  Yi-Che Lai ,  Shih-Kuang Chiu ,  Mao-Hua Yeh

IPC: H01L23/498 ,  H01L23/13 ,  H01L23/14 ,  H01L21/48 ,  H01L23/373

CPC classification number: H01L23/49827 ,  H01L21/481 ,  H01L21/4853 ,  H01L23/13 ,  H01L23/147 ,  H01L23/15 ,  H01L23/3738 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L2224/11

Abstract: A semiconductor package is provided, including a semiconductor substrate having a plurality of conductive vias, a buffer layer formed on the semiconductor substrate, a plurality of conductive pads formed on end surfaces of the conductive vias and covering the buffer layer. During a reflow process, the buffer layer greatly reduces the thermal stress, thereby eliminating the occurance of cracking at the interface of conductive pads. A method of fabricating such a semiconductor package is also provided.

公开(公告)号：US20170229386A1

公开(公告)日：2017-08-10

申请号：US15258303

申请日：2016-09-07

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Fang-Yu Liang ,  Hung-Hsien Chang ,  Yi-Che Lai ,  Wen-Tsung Tseng ,  Chen-Yu Huang

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49827 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/562 ,  H01L2224/73204 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A substrate structure is provided, including a substrate body having a conductive pad, an insulation layer formed on the substrate body and exposing the conductive pad, a conductive pillar disposed on the conductive pad, and a metal pad disposed on the insulation layer and electrically connected to the conductive pillar. A conductive component can be coupled to the metal pad. During a high-temperature process, the conductive pillar and the metal pad disperse the remaining stress generated due to heat, thereby preventing the conductive component from being cracked.

公开(公告)号：US09666536B2

公开(公告)日：2017-05-30

申请号：US14956758

申请日：2015-12-02

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yi-Wei Liu ,  Yan-Heng Chen ,  Mao-Hua Yeh ,  Hung-Wen Liu ,  Yi-Che Lai

IPC: H01L21/4763 ,  H01L23/538 ,  H01L21/683 ,  H01L21/56 ,  H01L21/78 ,  H01L21/3105 ,  H01L23/498 ,  H01L21/48 ,  H01L25/00 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L23/5389 ,  H01L21/31053 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68318 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2224/12105 ,  H01L2224/16235 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/15311

Abstract: The present invention provides a package structure and fabrication method thereof. The method includes providing a first carrier having a metal layer; forming a dielectric layer on the metal layer; forming a plurality of conductive pillars embedded into the dielectric layer and protruding from a surface of the dielectric layer, and disposing an electronic component on the surface of the dielectric layer; forming an encapsulating layer on the dielectric layer to encompass the plurality of conductive pillars, the dielectric layer and the electronic component; removing a portion of the encapsulating layer and the first carrier such that two ends of each of the plurality of conductive pillars are exposed from the encapsulating layer and the dielectric layer. Therefore, the present invention effectively reduces manufacturing costs and the need for an opening process while manufacturing the conductive pillars can be eliminated.

公开(公告)号：US09607974B2

公开(公告)日：2017-03-28

申请号：US14940554

申请日：2015-11-13

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chun-Tang Lin ,  Shih-Ching Chen ,  Yi-Che Lai ,  Hong-Da Chang ,  Hung-Wen Liu ,  Yi-Wei Liu ,  Hsi-Chang Hsu

IPC: H01L25/00 ,  H01L25/065 ,  H01L21/683 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/48 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/105 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/06548 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method for fabricating a package structure is provided, which includes: providing a first carrier having a circuit layer thereon; forming a plurality of conductive posts on the circuit layer and disposing at least an electronic element on the first carrier; forming an encapsulant on the first carrier to encapsulate the conductive posts, the circuit layer and the electronic element; and removing the first carrier, thereby dispensing with the conventional hole opening process for forming the conductive posts and hence reducing the fabrication costs.

公开(公告)号：US09607939B2

公开(公告)日：2017-03-28

申请号：US14259629

申请日：2014-04-23

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Wen-Tsung Tseng ,  Yi-Che Lai ,  Shih-Kuang Chiu ,  Mao-Hua Yeh

IPC: H01L21/768 ,  H01L23/498 ,  H01L23/14 ,  H01L23/15

CPC classification number: H01L23/49827 ,  H01L21/481 ,  H01L21/4853 ,  H01L23/13 ,  H01L23/147 ,  H01L23/15 ,  H01L23/3738 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L2224/11

Abstract: A semiconductor package is provided, including a semiconductor substrate having a plurality of conductive vias, a buffer layer formed on the semiconductor substrate, a plurality of conductive pads formed on end surfaces of the conductive vias and covering the buffer layer. During a reflow process, the buffer layer greatly reduces the thermal stress, thereby eliminating the occurance of cracking at the interface of conductive pads. A method of fabricating such a semiconductor package is also provided.

公开(公告)号：US09418874B2

公开(公告)日：2016-08-16

申请号：US14716272

申请日：2015-05-19

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Wan-Ting Chen ,  Mu-Hsuan Chan ,  Yi-Chian Liao ,  Chun-Tang Lin ,  Yi-Che Lai

IPC: H01L21/00 ,  H01L21/56 ,  H01L23/28 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01L21/78

CPC classification number: H01L21/561 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L21/78 ,  H01L23/28 ,  H01L23/31 ,  H01L23/3121 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5384 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/10253 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/81

Abstract: A semiconductor package is provided, including: a carrier; at least an interposer disposed on the carrier; an encapsulant formed on the carrier for encapsulating the interposer while exposing a top side of the interposer; a semiconductor element disposed on the top side of the interposer; and an adhesive formed between the interposer and the semiconductor element. By encapsulating the interposer with the encapsulant, warpage of the interposer is avoided and a planar surface is provided for the semiconductor element to be disposed thereon, thereby improving the reliability of electrical connection between the interposer and the semiconductor element.

Abstract translation: 提供半导体封装，包括：载体; 至少设置在所述载体上的插入件; 形成在所述载体上的密封剂，用于在暴露所述插入件的顶侧的同时封装所述插入件; 设置在所述插入件的顶侧的半导体元件; 以及形成在插入件和半导体元件之间的粘合剂。 通过用封装剂封装插入件，避免了插入器的翘曲，并且为了将半导体元件设置在其上提供平坦的表面，从而提高了插入件与半导体元件之间的电连接的可靠性。

公开(公告)号：US20160204093A1

公开(公告)日：2016-07-14

申请号：US15078418

申请日：2016-03-23

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chun-Tang Lin ,  Yi-Che Lai

IPC: H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/48 ,  H01L23/498 ,  H01L25/065 ,  H01L21/52 ,  H01L23/31

CPC classification number: H01L25/50 ,  H01L21/486 ,  H01L21/52 ,  H01L21/563 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/49833 ,  H01L25/065 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A fabrication method of a semiconductor package is disclosed, which includes the steps of: disposing a plurality of first semiconductor elements on an interposer; forming a first encapsulant on the interposer for encapsulating the first semiconductor elements; disposing a plurality of second semiconductor elements on the first semiconductor elements; forming a second encapsulant on the first semiconductor elements and the first encapsulant for encapsulating the second semiconductor elements; and thinning the interposer, thereby reducing the overall stack thickness and preventing warpage of the interposer.

Abstract translation: 公开了一种半导体封装的制造方法，其包括以下步骤：在插入件上设置多个第一半导体元件; 在所述插入件上形成用于封装所述第一半导体元件的第一密封剂; 在所述第一半导体元件上设置多个第二半导体元件; 在所述第一半导体元件和所述第一密封剂上形成用于封装所述第二半导体元件的第二密封剂; 并使插入件变薄，从而减小整体堆叠厚度并防止插入件的翘曲。

公开(公告)号：US20160190099A1

公开(公告)日：2016-06-30

申请号：US14956758

申请日：2015-12-02

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yi-Wei Liu ,  Yan-Heng Chen ,  Mao-Hua Yeh ,  Hung-Wen Liu ,  Yi-Che Lai

IPC: H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538 ,  H01L25/00 ,  H01L21/78 ,  H01L21/3105 ,  H01L23/31 ,  H01L21/683 ,  H01L21/768

CPC classification number: H01L23/5389 ,  H01L21/31053 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68318 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2224/12105 ,  H01L2224/16235 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/15311

Abstract: The present invention provides a package structure and fabrication method thereof. The method includes providing a first carrier having a metal layer; forming a dielectric layer on the metal layer; forming a plurality of conductive pillars embedded into the dielectric layer and protruding from a surface of the dielectric layer, and disposing an electronic component on the surface of the dielectric layer; forming an encapsulating layer on the dielectric layer to encompass the plurality of conductive pillars, the dielectric layer and the electronic component; removing a portion of the encapsulating layer and the first carrier such that two ends of each of the plurality of conductive pillars are exposed from the encapsulating layer and the dielectric layer. Therefore, the present invention effectively reduces manufacturing costs and the need for an opening process while manufacturing the conductive pillars can be eliminated.

Abstract translation: 本发明提供一种封装结构及其制造方法。 该方法包括提供具有金属层的第一载体; 在所述金属层上形成电介质层; 形成嵌入介电层并从电介质层的表面突出的多个导电柱，并在电介质层的表面上设置电子部件; 在所述电介质层上形成封装层以包围所述多个导电柱，所述电介质层和所述电子部件; 去除封装层和第一载体的一部分，使得多个导电柱中的每一个的两端从封装层和电介质层露出。 因此，本发明有效地降低了制造成本，并且可以消除在制造导电柱的过程中对打开过程的需要。