公开(公告)号：US20210343546A1

公开(公告)日：2021-11-04

申请号：US16895461

申请日：2020-06-08

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Yung-Ta Li ,  Yi-Chian Liao ,  Kong-Toon Ng ,  Chang-Fu Lin

IPC: H01L21/56 ,  H01L23/31 ,  H01L21/78 ,  H01L25/065

Abstract: An electronic package and a method for fabricating the same are provided. The electronic package includes a stepped recess formed at a peripheral portion of a packaging module to release stress of the electronic package.

公开(公告)号：US20140027926A1

公开(公告)日：2014-01-30

申请号：US13872468

申请日：2013-04-29

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Wang-Ting Chen ,  Mu-Hsuan Chan ,  Yi-Chian Liao ,  Chun-Tang Lin ,  Yi-Che Lai

IPC: H01L23/28 ,  H01L23/538 ,  H01L21/56

CPC classification number: H01L21/561 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L21/78 ,  H01L23/28 ,  H01L23/31 ,  H01L23/3121 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5384 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/10253 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/81

Abstract: A semiconductor package is provided, including: a carrier; at least an interposer disposed on the carrier; an encapsulant formed on the carrier for encapsulating the interposer while exposing a top side of the interposer; a semiconductor element disposed on the top side of the interposer; and an adhesive formed between the interposer and the semiconductor element. By encapsulating the interposer with the encapsulant, warpage of the interposer is avoided and a planar surface is provided for the semiconductor element to be disposed thereon, thereby improving the reliability of electrical connection between the interposer and the semiconductor element.

Abstract translation: 提供半导体封装，包括：载体; 至少设置在所述载体上的插入件; 形成在所述载体上的密封剂，用于在暴露所述插入件的顶侧的同时封装所述插入件; 设置在所述插入件的顶侧的半导体元件; 以及形成在插入件和半导体元件之间的粘合剂。 通过用封装剂封装插入件，避免了插入器的翘曲，并且为了将半导体元件设置在其上提供平坦的表面，从而提高了插入件与半导体元件之间的电连接的可靠性。

公开(公告)号：US09418874B2

公开(公告)日：2016-08-16

申请号：US14716272

申请日：2015-05-19

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Wan-Ting Chen ,  Mu-Hsuan Chan ,  Yi-Chian Liao ,  Chun-Tang Lin ,  Yi-Che Lai

IPC: H01L21/00 ,  H01L21/56 ,  H01L23/28 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01L21/78

CPC classification number: H01L21/561 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L21/78 ,  H01L23/28 ,  H01L23/31 ,  H01L23/3121 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5384 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/10253 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/81

Abstract: A semiconductor package is provided, including: a carrier; at least an interposer disposed on the carrier; an encapsulant formed on the carrier for encapsulating the interposer while exposing a top side of the interposer; a semiconductor element disposed on the top side of the interposer; and an adhesive formed between the interposer and the semiconductor element. By encapsulating the interposer with the encapsulant, warpage of the interposer is avoided and a planar surface is provided for the semiconductor element to be disposed thereon, thereby improving the reliability of electrical connection between the interposer and the semiconductor element.

Abstract translation: 提供半导体封装，包括：载体; 至少设置在所述载体上的插入件; 形成在所述载体上的密封剂，用于在暴露所述插入件的顶侧的同时封装所述插入件; 设置在所述插入件的顶侧的半导体元件; 以及形成在插入件和半导体元件之间的粘合剂。 通过用封装剂封装插入件，避免了插入器的翘曲，并且为了将半导体元件设置在其上提供平坦的表面，从而提高了插入件与半导体元件之间的电连接的可靠性。

公开(公告)号：US08829687B2

公开(公告)日：2014-09-09

申请号：US13722138

申请日：2012-12-20

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Mu-Hsuan Chan ,  Wan-Ting Chen ,  Yi-Chian Liao ,  Chun-Tang Lin ,  Yi-Chi Lai

IPC: H01L23/48 ,  H01L21/00 ,  H01L21/78 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/49811 ,  H01L21/486 ,  H01L21/78 ,  H01L23/147 ,  H01L23/49827 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/00

Abstract: A semiconductor package is provided, which includes: a semiconductor substrate having opposite first and second surfaces; an adhesive layer formed on the first surface of the semiconductor substrate; at least a semiconductor chip disposed on the adhesive layer; an encapsulant formed on the adhesive layer for encapsulating the semiconductor chip; and a plurality of conductive posts penetrating the first and second surfaces of the semiconductor substrate and the adhesive layer and electrically connected to the semiconductor chip, thereby effectively reducing the fabrication cost, shortening the fabrication time and improving the product reliability.

Abstract translation: 提供一种半导体封装，其包括：具有相反的第一和第二表面的半导体衬底; 形成在所述半导体衬底的第一表面上的粘合剂层; 至少设置在所述粘合剂层上的半导体芯片; 形成在用于封装半导体芯片的粘合剂层上的密封剂; 以及贯穿半导体衬底的第一和第二表面和粘合剂层并且电连接到半导体芯片的多个导电柱，从而有效地降低了制造成本，缩短了制造时间并提高了产品的可靠性。

公开(公告)号：US20140084455A1

公开(公告)日：2014-03-27

申请号：US13722138

申请日：2012-12-20

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Mu-Hsuan Chan ,  Wan-Ting Chen ,  Yi-Chian Liao ,  Chun-Tang Lin ,  Yi-Chi Lai

IPC: H01L23/498 ,  H01L21/78

CPC classification number: H01L23/49811 ,  H01L21/486 ,  H01L21/78 ,  H01L23/147 ,  H01L23/49827 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/00

Abstract: A semiconductor package is provided, which includes: a semiconductor substrate having opposite first and second surfaces; an adhesive layer formed on the first surface of the semiconductor substrate; at least a semiconductor chip disposed on the adhesive layer; an encapsulant formed on the adhesive layer for encapsulating the semiconductor chip; and a plurality of conductive posts penetrating the first and second surfaces of the semiconductor substrate and the adhesive layer and electrically connected to the semiconductor chip, thereby effectively reducing the fabrication cost, shortening the fabrication time and improving the product reliability.

Abstract translation: 提供一种半导体封装，其包括：具有相反的第一和第二表面的半导体衬底; 形成在所述半导体衬底的第一表面上的粘合剂层; 至少设置在所述粘合剂层上的半导体芯片; 形成在用于封装半导体芯片的粘合剂层上的密封剂; 以及贯穿半导体衬底的第一和第二表面和粘合剂层并且电连接到半导体芯片的多个导电柱，从而有效地降低了制造成本，缩短了制造时间并提高了产品的可靠性。

公开(公告)号：US11418002B2

公开(公告)日：2022-08-16

申请号：US16669796

申请日：2019-10-31

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Kong-Toon Ng ,  Yi-Chian Liao

IPC: G01N21/17 ,  H01S5/02234 ,  H01L23/538 ,  H01L23/00 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01S5/02355 ,  H04B10/50

Abstract: An electronic package and a method for fabricating an electronic package are provided. An encapsulation layer encapsulates a first electronic component and a plurality of conductive pillars, and is defined with a reservation region and a removal region adjacent to the reservation region. A circuit structure is disposed on the encapsulation layer. The removal region and the circuit structure therewithin are removed for an optical communication element to protrude from a lateral surface of the encapsulation layer when the optical communication element is disposed on the circuit structure, so as to avoid a packaging material used in a subsequent process from being adhered to a protruding portion of the optical communication element.

公开(公告)号：US20210066883A1

公开(公告)日：2021-03-04

申请号：US16669796

申请日：2019-10-31

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Kong-Toon Ng ,  Yi-Chian Liao

IPC: H01S5/022 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56

Abstract: An electronic package and a method for fabricating an electronic package are provided. An encapsulation layer encapsulates a first electronic component and a plurality of conductive pillars, and is defined with a reservation region and a removal region adjacent to the reservation region. A circuit structure is disposed on the encapsulation layer. The removal region and the circuit structure therewithin are removed for an optical communication element to protrude from a lateral surface of the encapsulation layer when the optical communication element is disposed on the circuit structure, so as to avoid a packaging material used in a subsequent process from being adhered to a protruding portion of the optical communication element.

公开(公告)号：US09548220B2

公开(公告)日：2017-01-17

申请号：US14986903

申请日：2016-01-04

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Kuan-Wei Chuang ,  Chun-Tang Lin ,  Yi-Chian Liao ,  Yi-Che Lai

IPC: H01L21/48 ,  H01L21/58 ,  H01L23/498 ,  H01L21/78 ,  H01L23/00 ,  H01L23/14 ,  H01L21/311 ,  H01L21/56 ,  H01L21/683 ,  H01L25/00

CPC classification number: H01L21/486 ,  H01L21/31111 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/147 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49872 ,  H01L24/03 ,  H01L24/08 ,  H01L24/11 ,  H01L24/17 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/02317 ,  H01L2224/02372 ,  H01L2224/03002 ,  H01L2224/08235 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2924/351 ,  H01L2924/00

Abstract: A method of fabricating a semiconductor package is provided, including: cutting a substrate into a plurality of interposers; disposing the interposers in a plurality of openings of a carrier, wherein the openings are spaced from one another by a distance; forming a first encapsulant to encapsulate the interposers; removing the carrier; and disposing at least a semiconductor element on each of the interposers. By cutting the substrate first, good interposers can be selected and rearranged such that finished packages can be prevented from being wasted due to inferior interposers.

Abstract translation: 提供一种制造半导体封装的方法，包括：将衬底切割成多个中介层; 将所述插入件布置在载体的多个开口中，其中所述开口彼此间隔一定距离; 形成第一密封剂以封装所述插入件; 移除载体; 以及在每个所述插入件上设置至少一个半导体元件。 通过首先切割基板，可以选择和重新布置良好的插入件，从而可以防止由于不良插入件浪费完成的封装。

公开(公告)号：US09087780B2

公开(公告)日：2015-07-21

申请号：US13872468

申请日：2013-04-29

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Wan-Ting Chen ,  Mu-Hsuan Chan ,  Yi-Chian Liao ,  Chun-Tang Lin ,  Yi-Che Lai

IPC: H01L23/48 ,  H01L23/28 ,  H01L21/56 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L21/561 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L21/78 ,  H01L23/28 ,  H01L23/31 ,  H01L23/3121 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5384 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/10253 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/81

Abstract: A semiconductor package is provided, including: a carrier; at least an interposer disposed on the carrier; an encapsulant formed on the carrier for encapsulating the interposer while exposing a top side of the interposer; a semiconductor element disposed on the top side of the interposer; and an adhesive formed between the interposer and the semiconductor element. By encapsulating the interposer with the encapsulant, warpage of the interposer is avoided and a planar surface is provided for the semiconductor element to be disposed thereon, thereby improving the reliability of electrical connection between the interposer and the semiconductor element.

Abstract translation: 提供半导体封装，包括：载体; 至少设置在所述载体上的插入件; 形成在所述载体上的密封剂，用于在暴露所述插入件的顶侧的同时封装所述插入件; 设置在所述插入件的顶侧的半导体元件; 以及形成在插入件和半导体元件之间的粘合剂。 通过用封装剂封装插入件，避免了插入器的翘曲，并且为了将半导体元件设置在其上提供平坦的表面，从而提高了插入件与半导体元件之间的电连接的可靠性。

公开(公告)号：US11164755B1

公开(公告)日：2021-11-02

申请号：US16895461

申请日：2020-06-08

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Yung-Ta Li ,  Yi-Chian Liao ,  Kong-Toon Ng ,  Chang-Fu Lin

IPC: H01L21/56 ,  H01L23/31 ,  H01L21/78 ,  H01L25/065 ,  H01L23/00

Abstract: An electronic package and a method for fabricating the same are provided. The electronic package includes a stepped recess formed at a peripheral portion of a packaging module to release stress of the electronic package.