公开(公告)号：US10396188B1

公开(公告)日：2019-08-27

申请号：US15962859

申请日：2018-04-25

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Gengming Tao ,  Xia Li

IPC: H01L29/66 ,  H01L29/737 ,  H01L27/082 ,  H01L29/205 ,  H01L29/06

Abstract: A semiconductor device comprises a heterojunction bipolar transistor (HBT). The HBT comprises an emitter, a collector, and a base between the emitter and the collector. A width of the emitter may be smaller than 100 nanometers, which is suitable for high speed applications.

公开(公告)号：US20190019538A1

公开(公告)日：2019-01-17

申请号：US15817441

申请日：2017-11-20

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang ,  Gengming Tao

IPC: G11C5/02 ,  G11C5/06 ,  G11C7/18 ,  G11C7/12 ,  G11C8/08 ,  G06N3/08

CPC classification number: G11C5/02 ,  G06N3/049 ,  G06N3/063 ,  G06N3/0635 ,  G06N3/08 ,  G06N3/088 ,  G11C5/063 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/18 ,  G11C8/08 ,  G11C11/161 ,  G11C11/223 ,  G11C11/54 ,  G11C13/0002 ,  G11C16/0483 ,  H03K19/18

Abstract: Non-volatile (NV) memory (NVM) matrix circuits employing NVM circuits for performing matrix computations are disclosed. In exemplary aspects disclosed herein, an NVM matrix circuit is provided that has a plurality of NVM storage string circuits each comprising a plurality of NVM bit cell circuits each configured to store a memory state. Each NVM bit cell circuit has a stored memory state represented by a resistance, and includes a transistor whose gate node is coupled to a word line among a plurality of word lines configured to receive an input vector of 1×m size for example. Activation of the gate of a given NVM bit cell circuit controls whether its resistance is contributed to a respective source line. This causes a summation current to be generated on each source line based on the weighted summed contribution of each NVM bit cell circuit's resistance to its respective source line.

公开(公告)号：US09601617B2

公开(公告)日：2017-03-21

申请号：US14604544

申请日：2015-01-23

Applicant: QUALCOMM Incorporated

Inventor： Jun Yuan ,  Xia Li ,  Bin Yang

IPC: H01L29/78 ,  H01L29/161 ,  H01L29/66 ,  H01L29/51 ,  H01L29/49 ,  H01L21/28 ,  H01L29/739

CPC classification number: H01L29/7827 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/161 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66356 ,  H01L29/66666 ,  H01L29/66977 ,  H01L29/7391

Abstract: In a particular embodiment, an apparatus includes an electron tunnel structure. The electron tunnel structure includes a tunneling layer, a channel layer, a source layer, and a drain layer. The tunneling layer and the channel layer are positioned between the source layer and the drain layer. The transistor device further includes a high-k dielectric layer adjacent to the electron tunnel structure.

公开(公告)号：US09236483B2

公开(公告)日：2016-01-12

申请号：US14179311

申请日：2014-02-12

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Xia Li ,  Pr Chidambaram ,  Choh Fei Yeap

IPC: H01L29/76 ,  H01L29/94 ,  H01L29/78 ,  H01L29/267 ,  H01L29/06 ,  H01L29/66 ,  H03K17/687

CPC classification number: H01L29/7855 ,  H01L29/0607 ,  H01L29/267 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/7851 ,  H03K17/687 ,  H03K2017/6878 ,  H03K2217/0018 ,  H03K2217/0054

Abstract: A FinFET having a backgate and a barrier layer beneath the fin channel of the FinFET, where the barrier layer has a bandgap greater than that of the backgate. The barrier layer serves as an etch stop layer under the fin channel, resulting in reduced fin channel height variation. The backgate provides improved current control. There is less punchthrough due to the higher bandgap barrier layer. The FinFET may also include deeply embedded stressors adjacent to the source/drain diffusions through the high bandgap barrier layer.

Abstract translation: 在FinFET的鳍通道下方具有背栅和阻挡层的FinFET，其中阻挡层的带隙大于背栅的带隙。 阻挡层在翅片通道下面用作蚀刻停止层，从而减少了翅片通道高度变化。 后门提供改进的电流控制。 由于较高的带隙阻挡层，穿孔较少。 FinFET还可以包括通过高带隙势垒层与源极/漏极扩散相邻的深埋入的应力源。

公开(公告)号：US09111635B2

公开(公告)日：2015-08-18

申请号：US13869110

申请日：2013-04-24

Applicant: QUALCOMM Incorporated ,  Industry-Academic Cooperation Foundation, Yonsei University

Inventor： Seong-Ook Jung ,  Younghwi Yang ,  Bin Yang ,  Zhongze Wang ,  Choh fei Yeap

IPC: G11C11/00 ,  G11C11/412 ,  G11C11/419

CPC classification number: G11C11/412 ,  G11C11/417 ,  G11C11/419 ,  H01L27/0207 ,  H01L27/1104 ,  Y10T29/41

Abstract: Static random access memories (SRAM) with read-preferred cell structures and write drivers are disclosed. In one embodiment, the SRAM has a six transistor bit cell. The read-preferred bit cell is implemented by providing two inverters, each having a pull up transistor, a pull down transistor and a pass gate transistor. Each pull up transistor is associated with a feedback loop. The feedback loop improves random static noise margin. Each transistor has a width and a length. The lengths of the pass gate transistors are increased. The widths of the pull down transistors are equal to one another and also equal to the widths of the pass gate transistors. The widths of the pass gate and pull down transistors may also be increased relative to prior designs. A write assist circuit may also be used to improve performance.

Abstract translation: 公开了具有读优选单元结构和写驱动器的静态随机存取存储器（SRAM）。 在一个实施例中，SRAM具有六个晶体管位单元。 读优选位单元通过提供两个反相器来实现，每个反相器具有上拉晶体管，下拉晶体管和通过栅极晶体管。 每个上拉晶体管与反馈回路相关联。 反馈环路改善了随机的静态噪声容限。 每个晶体管具有宽度和长度。 传输栅晶体管的长度增加。 下拉晶体管的宽度彼此相等，并且也等于通过栅极晶体管的宽度。 通过栅极和下拉晶体管的宽度也可以相对于现有设计而增加。 也可以使用写辅助电路来提高性能。

公开(公告)号：US20150162405A1

公开(公告)日：2015-06-11

申请号：US14100760

申请日：2013-12-09

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Xia Li ,  PR Chidambaram

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/205

CPC classification number: H01L29/1045 ,  H01L21/743 ,  H01L29/1054 ,  H01L29/1087 ,  H01L29/205 ,  H01L29/66522 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/7848 ,  H01L29/785

Abstract: An apparatus comprises a substrate. The apparatus also comprises a diffusion barrier formed on a surface of a first region of the substrate. The diffusion barrier is formed using a first material having a first band gap energy. The apparatus further comprises a channel region formed on a surface of the diffusion barrier. The channel region is formed using a second material having a second band gap energy that is lower than the first band gap energy. The apparatus further comprises a back gate contact coupled to the first region of the substrate.

Abstract translation: 一种装置包括基板。 该装置还包括形成在基板的第一区域的表面上的扩散阻挡层。 使用具有第一带隙能量的第一材料形成扩散阻挡层。 该装置还包括形成在扩散阻挡层的表面上的沟道区。 沟道区域使用具有低于第一带隙能量的第二带隙能量的第二材料形成。 该装置还包括耦合到衬底的第一区域的背栅极接触。

公开(公告)号：US09047960B2

公开(公告)日：2015-06-02

申请号：US13957460

申请日：2013-08-02

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang ,  Zhongze Wang

IPC: G11C16/00 ,  G11C16/10 ,  H01L21/28 ,  H01L29/66 ,  G11C16/14

CPC classification number: G11C16/10 ,  G11C16/0433 ,  G11C16/14 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

Abstract: An apparatus includes a storage transistor. The storage transistor includes a floating gate configured to store electrical charge and a control gate. The floating gate is coupled to the control gate via capacitive coupling. The floating gate and the control gate are metal. The apparatus also includes an access transistor coupled to the storage transistor. A gate of the access transistor is coupled to a word line. The storage transistor and the access transistor are serially coupled between a bit line and a source line.

Abstract translation: 一种装置包括存储晶体管。 存储晶体管包括被配置为存储电荷的浮动栅极和控制栅极。 浮动栅极通过电容耦合耦合到控制栅极。 浮动门和控制门是金属的。 该装置还包括耦合到存储晶体管的存取晶体管。 存取晶体管的栅极耦合到字线。 存储晶体管和存取晶体管串联耦合在位线和源极线之间。

公开(公告)号：US09012966B2

公开(公告)日：2015-04-21

申请号：US13684059

申请日：2012-11-21

Applicant: QUALCOMM Incorporated

Inventor： PR Chidambaram ,  Bin Yang

IPC: H01L27/108 ,  H01L29/94 ,  H01L49/02 ,  H01L23/522 ,  H01L27/06

CPC classification number: H01L27/0629 ,  H01L23/5223 ,  H01L23/5228 ,  H01L28/20 ,  H01L28/40 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating a metal-insulator-metal (MIM) capacito includes depositing a first middle of line (MOL) conductive layer over a shallow trench isolation (STI) region of a semiconductor substrate. The first MOL conductive layer provides a first plate of the MIM capacitor as well as a first set of local interconnects to source and drain regions of a semiconductor device. The method also includes depositing an insulator layer on the first MOL conductive layer as a dielectric layer of the MIM capacitor. The method further includes depositing a second MOL conductive layer on the insulator layer as a second plate of the MIM capacitor.

Abstract translation: 一种用于制造金属 - 绝缘体 - 金属（MIM）电容的方法，包括在半导体衬底的浅沟槽隔离（STI）区域上沉积第一中间线（MOL）导电层。 第一MOL导电层提供MIM电容器的第一板以及到半导体器件的源极和漏极区域的第一组局部互连。 该方法还包括在第一MOL导电层上沉积绝缘体层作为MIM电容器的电介质层。 所述方法还包括在所述绝缘体层上沉积作为所述MIM电容器的第二板的第二MOL导电层。

公开(公告)号：US20150069458A1

公开(公告)日：2015-03-12

申请号：US14021795

申请日：2013-09-09

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Ming Cai ,  Bin Yang

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66977 ,  H01L29/66356 ,  H01L29/66795 ,  H01L29/7391 ,  H01L29/7827

Abstract: A tunnel field transistor (TFET) device includes a fin structure that protrudes from a substrate surface. The fin structure includes a base portion proximate to the substrate surface, a top portion, and a first pair of sidewalls extending from the base portion to the top portion. The first pair of sidewalls has a length corresponding to a length of the fin structure. The fin structure also includes a first doped region having a first dopant concentration at the base portion of the fin structure. The fin structure also includes a second doped region having a second dopant concentration at the top portion of the fin structure. The TFET device further includes a gate including a first conductive structure neighboring a first sidewall of the first pair of sidewalls. A dielectric layer electrically isolates the first conductive structure from the first sidewall.

Abstract translation: 隧道场晶体管（TFET）器件包括从衬底表面突出的鳍结构。 翅片结构包括靠近基底表面的基部，顶部和从基部延伸到顶部的第一对侧壁。 第一对侧壁的长度对应于翅片结构的长度。 翅片结构还包括在鳍结构的基部处具有第一掺杂剂浓度的第一掺杂区域。 鳍结构还包括在鳍结构的顶部具有第二掺杂剂浓度的第二掺杂区。 TFET器件还包括栅极，其包括与第一对侧壁的第一侧壁相邻的第一导电结构。 电介质层将第一导电结构与第一侧壁电隔离。

公开(公告)号：US08942034B2

公开(公告)日：2015-01-27

申请号：US13759344

申请日：2013-02-05

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang

IPC: G11C16/04 ,  G11C5/06 ,  G11C7/12 ,  G06F17/50 ,  G11C11/40 ,  G11C17/16 ,  G11C11/404 ,  G11C5/14

CPC classification number: G11C17/18 ,  G06F17/5045 ,  G11C5/06 ,  G11C5/146 ,  G11C7/12 ,  G11C11/40 ,  G11C11/404 ,  G11C11/5692 ,  G11C16/04 ,  G11C17/16 ,  G11C2211/4016

Abstract: A method includes selectively creating a first breakdown condition and a second breakdown condition at a semiconductor transistor structure. The first breakdown condition is between a source overlap region of the semiconductor transistor structure and a gate of the semiconductor transistor structure. The second breakdown condition is between ad rain overlap region of the semiconductor transistor structure and the gate.

Abstract translation: 一种方法包括在半导体晶体管结构中选择性地产生第一击穿条件和第二击穿条件。 第一击穿条件在半导体晶体管结构的源极重叠区域和半导体晶体管结构的栅极之间。 第二击穿条件是在半导体晶体管结构的覆盖区域和栅极之间。