公开(公告)号：US20190096786A1

公开(公告)日：2019-03-28

申请号：US16204543

申请日：2018-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： JaeHong PARK ,  Hanhong LEE ,  Sungwoo JOO ,  Woon-young BAEK

IPC: H01L23/433 ,  H01L23/04 ,  H01L23/427 ,  H01L23/053 ,  H01L25/065 ,  H01L23/544 ,  H01L23/00 ,  H01L23/40

CPC classification number: H01L23/433 ,  H01L23/04 ,  H01L23/053 ,  H01L23/427 ,  H01L23/4334 ,  H01L23/544 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2023/4068 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2924/1434 ,  H01L2924/15162 ,  H01L2924/15311 ,  H01L2924/16251 ,  H01L2924/166 ,  H01L2924/18161 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor package includes a package substrate including a fastening section at one end and a connecting terminal section at an opposite end, at least one semiconductor device mounted on the package substrate, at least one heat pipe on the at least one semiconductor device, and a lid on the at least one semiconductor device and the at least one heat pipe. At least one end of the heat pipe is between the at least one semiconductor device and either the fastening section or the connecting terminal section.

公开(公告)号：US20150163958A1

公开(公告)日：2015-06-11

申请号：US14407257

申请日：2013-06-06

Applicant: KANEKA CORPORATION

Inventor： Keisuke Oguma ,  Aki Koukami ,  Kazuo Hagiwara

IPC: H05K7/20 ,  C08L71/02 ,  B29C73/02 ,  C08L33/00

CPC classification number: H05K7/2039 ,  B29C73/02 ,  C08L33/00 ,  C08L71/02 ,  H01L23/295 ,  H01L23/3121 ,  H01L23/3737 ,  H01L23/42 ,  H01L23/552 ,  H01L25/0655 ,  H01L2924/0002 ,  H01L2924/16151 ,  H01L2924/16251 ,  H01L2924/166 ,  H01L2924/3025 ,  H05K7/20463 ,  H05K9/0024 ,  H01L2924/00

Abstract: The present invention provides a heat dissipation structure that does not cause problems such as contact failures in electronic components and that is applicable to electronic components with high heat densities. The present invention also provides a method for easily repairing an electronic device. The heat dissipation structure is obtained by filling and curing a thermally conductive curable resin composition in an electromagnetic shielding case on a substrate on which an electronic component with a heat density of 0.2 W/cm2 to 500 W/cm2 is mounted, the thermally conductive curable resin composition containing a curable liquid resin (I) and a thermally conductive filler (II), having a viscosity at 23° C. of 30 Pa·s to 3000 Pa·s and a thermal conductivity of 0.5 W/(m·K) or more, and being curable by moisture or heat.

Abstract translation: 本发明提供一种散热结构，其不会引起电子部件的接触不良等问题，适用于高密度的电子部件。 本发明还提供一种易于修复电子设备的方法。 通过在其上安装有热密度为0.2W / cm 2至500W / cm 2的电子部件的基板上的电磁屏蔽壳体中填充和固化导热性固化性树脂组合物，获得散热结构， 在23℃下的粘度为30Pa·s〜3000Pa·s，导热率为0.5W /（m·K）的含有固化型液态树脂（I）和导热性填料（II）的树脂组合物， 或更多，并且可通过水分或热量固化。

公开(公告)号：US20130256847A1

公开(公告)日：2013-10-03

申请号：US13778467

申请日：2013-02-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Su-Min PARK ,  Jong-Ho LEE

IPC: H01L23/58 ,  H01L21/50

CPC classification number: H01L21/4817 ,  H01L21/50 ,  H01L23/552 ,  H01L23/585 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/166 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: Provided are a semiconductor device including an EMI shield, a method of manufacturing the same, a semiconductor module including the semiconductor device, and an electronic system including the semiconductor device. The semiconductor device includes a lower semiconductor package, an upper semiconductor package, a package bump, and an EMI shield. The lower semiconductor package includes a lower substrate, a lower semiconductor chip mounted on the lower substrate, and a ground wire separated from the lower semiconductor chip. The upper semiconductor package includes an upper substrate stacked on the lower semiconductor package, and an upper semiconductor chip stacked on the upper substrate. The package bump electrically connects the upper semiconductor package and the lower semiconductor package. The EMI shield covers the upper and lower semiconductor packages and is electrically connected to the ground wire.

公开(公告)号：US08274797B2

公开(公告)日：2012-09-25

申请号：US12674694

申请日：2009-02-18

Applicant: Kazuyuki Ono ,  Yoshio Tanaka ,  Kiyoshi Nakajima ,  Naoto Kuratani ,  Tomofumi Maekawa

Inventor： Kazuyuki Ono ,  Yoshio Tanaka ,  Kiyoshi Nakajima ,  Naoto Kuratani ,  Tomofumi Maekawa

IPC: H05K7/00

CPC classification number: H01L23/12 ,  H01L23/055 ,  H01L23/13 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/16235 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2224/48599 ,  H01L2224/48644 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/85444 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1433 ,  H01L2924/16152 ,  H01L2924/166 ,  H05K3/305 ,  H05K9/0026 ,  H05K2201/09036 ,  H01L2924/00014 ,  H01L2924/0715 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An electronic component has a printed substrate having a die bonding portion, a semiconductor element rigidly bonded to the die bonding portion of the printed substrate by a die bonding resin, and a wire bonding terminal formed by a conductor pattern on the printed substrate that is connected to the semiconductor element by a bonding wire. A groove portion located at a level lower than the conductor pattern of the printed substrate is formed in a region located on at least a die bonding portion side in a region surrounding the wire bonding terminal.

Abstract translation: 电子部件具有印刷基板，其具有芯片接合部，通过芯片接合树脂与印刷基板的芯片接合部分刚性地接合的半导体元件，以及通过印刷基板上的导体图案形成的引线接合端子，所述导线图案被连接 通过接合线连接到半导体元件。 在位于引线接合端子周围的区域中的至少芯片接合部侧的区域中，形成位于比印刷基板的导体图案低的位置的槽部。

公开(公告)号：US08164181B2

公开(公告)日：2012-04-24

申请号：US12872131

申请日：2010-08-31

Applicant: Kazuhiro Tashiro ,  Keisuke Fukuda ,  Naohito Kohashi ,  Shigeyuki Maruyama

Inventor： Kazuhiro Tashiro ,  Keisuke Fukuda ,  Naohito Kohashi ,  Shigeyuki Maruyama

IPC: H01L23/12

CPC classification number: H01L21/67333 ,  H01L21/50 ,  H01L22/20 ,  H01L23/04 ,  H01L23/544 ,  H01L25/0655 ,  H01L2223/54473 ,  H01L2924/0002 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/16153 ,  H01L2924/1616 ,  H01L2924/166 ,  Y10T29/49826 ,  H01L2924/00

Abstract: A semiconductor device packaging structure is disclosed that can improve reliability of a performance test for the semiconductor device and prevent damage to the semiconductor device during transportation or packaging for shipment. An IC cover is attached to the semiconductor device, which has height unevenness because it includes semiconductor chips and electric parts having different heights. The IC cover includes projecting portions and a base portion. After being attached to the semiconductor device, the projecting portions stand in a free area in the semiconductor device, and the base portion is supported by the projections to be separated from the semiconductor chips and electric parts in the semiconductor device. The IC cover is detachably attached to the semiconductor device.

Abstract translation: 公开了一种半导体器件封装结构，其可以提高半导体器件的性能测试的可靠性，并防止在运输或包装期间对半导体器件的损坏。 由于包含半导体芯片和具有不同高度的电气部件，所以具有高度不均匀性的半导体器件附着IC盖。 IC盖包括突出部分和基部。 在安装到半导体器件之后，突出部分位于半导体器件中的自由区域中，并且基底部分由与半导体芯片和半导体器件中的电气部件分离的突起支撑。 IC盖可拆卸地附接到半导体器件。

公开(公告)号：US20120061852A1

公开(公告)日：2012-03-15

申请号：US12878795

申请日：2010-09-09

Applicant: Michael Z. Su ,  Gamal Refai-Ahmed ,  Bryan Black

Inventor： Michael Z. Su ,  Gamal Refai-Ahmed ,  Bryan Black

IPC: H01L23/48 ,  H01L21/50

CPC classification number: H01L23/24 ,  H01L21/563 ,  H01L23/147 ,  H01L23/293 ,  H01L23/295 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/49575 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83051 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16251 ,  H01L2924/166 ,  H01L2924/167 ,  H01L2924/00

Abstract: A method of manufacturing is provided that includes providing a semiconductor chip with an insulating layer. The insulating layer includes a trench. A second semiconductor chip is stacked on the first semiconductor chip to leave a gap. A polymeric filler is placed in the gap wherein a portion of the polymeric filler is drawn into the trench.

Abstract translation: 提供一种制造方法，其包括为半导体芯片提供绝缘层。 绝缘层包括沟槽。 第二半导体芯片堆叠在第一半导体芯片上以留下间隙。 将聚合物填料放置在间隙中，其中一部分聚合物填料被拉入沟槽。

公开(公告)号：US20120061133A1

公开(公告)日：2012-03-15

申请号：US13157499

申请日：2011-06-10

Applicant: Satoshi MASUDA

Inventor： Satoshi MASUDA

IPC: H05K1/11

CPC classification number: H01L23/057 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49861 ,  H01L23/66 ,  H01L2223/6611 ,  H01L2223/6627 ,  H01L2223/6633 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/16152 ,  H01L2924/166 ,  H01L2924/167 ,  H01L2924/16787 ,  H01L2924/1903 ,  H01L2924/19033 ,  H01L2924/19039 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01P3/006 ,  H01P5/028 ,  H01L2924/00

Abstract: A high-frequency circuit package including a dielectric substrate; a signal line, a first ground conductor layer, a second ground conductor layer, and a frame-shaped dielectric layer formed on the dielectric substrate; a third ground conductor layer formed on the frame-shaped dielectric layer; a first recess formed in the frame-shaped dielectric layer and including a first surface and a second surface that are located above the first ground conductor layer and the second ground conductor layer and extend laterally at an oblique angle with respect to the length direction of the signal line; a first ground line formed on the first surface and electrically connecting the first ground conductor layer with the third ground conductor layer; and a second ground line formed on the second surface and electrically connecting the second ground conductor layer with the third ground conductor layer.

Abstract translation: 一种包括电介质基片的高频电路封装; 信号线，第一接地导体层，第二接地导体层和形成在电介质基板上的框状电介质层; 形成在所述框状电介质层上的第三接地导体层; 形成在所述框状电介质层中并且包括第一表面和第二表面的第一凹部，所述第一表面和第二表面位于所述第一接地导体层和所述第二接地导体层之上，并且相对于所述第一接地导体层的长度方向以倾斜角横向延伸 信号线 形成在所述第一表面上并将所述第一接地导体层与所述第三接地导体层电连接的第一接地线; 以及第二接地线，形成在所述第二表面上并将所述第二接地导体层与所述第三接地导体层电连接。

公开(公告)号：US08058106B2

公开(公告)日：2011-11-15

申请号：US12584428

申请日：2009-09-04

Applicant: Mei-Ling Wu ,  Rueyshing Star Huang

Inventor： Mei-Ling Wu ,  Rueyshing Star Huang

IPC: H01L21/00 ,  H01L23/02

CPC classification number: H01L21/50 ,  B81C1/00269 ,  B81C2203/0109 ,  B81C2203/035 ,  H01L23/10 ,  H01L24/28 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/49 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/078 ,  H01L2924/10158 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/16152 ,  H01L2924/163 ,  H01L2924/166 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: In a method of vacuum packaging a MEMS device, at least one MEMS device is attached on a substrate. A solder preform is printed on the substrate at the perimeter surrounding the substrate. A lid is attached to the solder preform wherein the lid provides a cavity enclosing the at least one MEMS device. A first reflowing step reflows the solder at a first temperature, partially sealing the lid/substrate interface and at the same time does the outgassing and baking procedure for the packaging. Flux is applied onto an outer ring of the solder preform and a second step reflows the solder at a second temperature, completely sealing the lid/substrate interface and providing a vacuum cavity enclosing the at least one MEMS device.

Abstract translation: 在真空封装MEMS器件的方法中，至少一个MEMS器件附接在衬底上。 焊料预制件在围绕衬底的周边处印刷在衬底上。 盖子附接到焊料预成型件，其中盖子提供封闭至少一个MEMS器件的空腔。 第一回流步骤在第一温度下回流焊料，部分地密封盖/基底界面，同时对包装进行除气和烘烤程序。 焊剂被施加到焊料预制件的外环上，第二步骤在第二温度下回流焊料，完全密封盖/衬底界面并提供封闭至少一个MEMS器件的真空腔。

公开(公告)号：US20110210431A1

公开(公告)日：2011-09-01

申请号：US13015010

申请日：2011-01-27

Applicant: Emmanuel LOISELET

Inventor： Emmanuel LOISELET

IPC: H01L23/495 ,  H01L21/60

CPC classification number: H01L23/045 ,  H01L23/049 ,  H01L23/10 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6622 ,  H01L2223/6627 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/4911 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1576 ,  H01L2924/166 ,  H01L2924/1903 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/3025 ,  H01P1/387 ,  H05K5/069 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A microwave circuit package having a ball grid array, BGA, soldered on to a planar major surface of a metal housing of the package for the electrical connection of the ports of the microwave circuit through RF signal paths to an adjacent electrical device. Each of the RF signal paths comprises a pin electrically connected to a respective port of the microwave circuit package, projecting normally through an opening in the said major surface from which it is electrically insulated, and soldered to a ball of the BGA; the pin and the surrounding balls of the BGA, which are soldered to the metal housing, constituting a coaxial RF signal path.

Abstract translation: 一种具有球栅阵列BGA的微波电路封装，其焊接在封装的金属外壳的平面主表面上，用于通过RF信号路径将微波电路的端口电连接到相邻的电气设备。 每个RF信号路径包括电连接到微波电路封装的相应端口的引脚，其正常通过所述主表面中的电绝缘突出并焊接到BGA的球; 焊接到金属外壳的BGA的引脚和周围的球构成同轴的RF信号路径。

公开(公告)号：US07768360B2

公开(公告)日：2010-08-03

申请号：US11649433

申请日：2007-01-04

Applicant: Sehat Sutardja

Inventor： Sehat Sutardja

IPC: H03L1/00

CPC classification number: H03L1/027 ,  B82Y10/00 ,  G11C7/04 ,  G11C7/22 ,  G11C7/222 ,  G11C29/028 ,  G11C2029/5002 ,  G11C2207/2254 ,  H01L23/315 ,  H01L23/34 ,  H01L2224/05553 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2924/01046 ,  H01L2924/1461 ,  H01L2924/16235 ,  H01L2924/166 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H03B5/04 ,  H03B5/30 ,  H03L1/026 ,  H03L5/00 ,  H03L7/08 ,  H03L7/0802 ,  H03L7/0891 ,  H03L7/197 ,  H03L7/1974 ,  H03L7/1976 ,  H01L2924/00

Abstract: A crystal oscillator emulator integrated circuit, comprises a first temperature sensor that senses a first temperature of the integrated circuit; memory that stores calibration parameters and that selects at least one of the calibration parameters based on the first temperature; a semiconductor oscillator that generates an output signal having a frequency that is based on the calibration parameters; and an adaptive calibration circuit that adaptively adjusts a calibration approach for generating the calibration parameters based on a number of temperature test points input thereto.

Abstract translation: 一种晶体振荡器仿真器集成电路，包括：感测集成电路的第一温度的第一温度传感器; 存储器，其存储校准参数并且基于第一温度选择至少一个校准参数; 半导体振荡器，其产生具有基于所述校准参数的频率的输出信号; 以及自适应校准电路，其自适应地调整用于基于输入到其的温度测试点的数量来生成校准参数的校准方法。