公开(公告)号：US20240356499A1

公开(公告)日：2024-10-24

申请号：US18622565

申请日：2024-03-29

申请人： Sehat Sutardja

发明人： Sehat Sutardja

IPC分类号： H03F1/56 ,  H03F3/24

CPC分类号： H03F1/565 ,  H03F3/245 ,  H03F2200/222 ,  H03F2200/387 ,  H03F2200/451

摘要： An amplifier system comprising an input matching network configured to receive an input signal from a signal source. The input matching network is configured to impedance match between the amplifier system and the signal source. An input transformer is configured to receive the impedance matched input signal and perform voltage step down and current step up. An amplifier is configured to receive and amplify an output signal from the input transformer to generate an amplified signal. A low winding ratio output transformer provides isolation between an antenna and amplifier. An output matching network is configured to impedance match to an antenna and provide voltage step up. The input transformer may have a ratio of 2N:N, such as 2:1 ratio. At least one center tap of the input transformer may connect to a bias voltage. The amplifier system may be configured for operation in the radio frequency band.

公开(公告)号：US20240256222A1

公开(公告)日：2024-08-01

申请号：US18423214

申请日：2024-01-25

申请人： Sehat Sutardja

发明人： Sehat Sutardja

IPC分类号： G06F7/506 ,  H03K19/00

CPC分类号： G06F7/506 ,  H03K19/00

摘要： Apparatus and method to logically process signals representative of multiple-bit numbers include successively delaying applications of the bit-representative signals to logical processing stages from associated input registers by a delay interval between input registers that is substantially equal to the processing delay interval per bit-level of the logical processing stage. In this way, successively more significant bits of each of plural numbers being logically processed are validly available for processing at each bit-level logic stage after a delay. At least one of the bit-representative signals is inverted prior to the input registers or prior to processing by the logical processing stage. The delay is reduced by omitting an inverting function in a carry circuit associated with at least one logical processing stage. Similarly, output registers for latching the logic output of each bit-level logic stage are clocked at successively delayed intervals substantially equal to the processing delay interval.

公开(公告)号：US20230154674A1

公开(公告)日：2023-05-18

申请号：US17974434

申请日：2022-10-26

申请人： Sehat Sutardja

发明人： Sehat Sutardja

IPC分类号： H01F27/36 ,  H03H7/38 ,  H01F27/28 ,  H01F17/00 ,  H01F19/04 ,  H01F27/32

CPC分类号： H01F27/363 ,  H03H7/38 ,  H01F27/2804 ,  H01F17/0013 ,  H01F19/04 ,  H01F27/32 ,  H01F27/36 ,  H01F27/288

摘要： A transformer comprising a primary winding and a secondary winding. The primary winding has N2 number turns and having a first terminal and a second terminal. The secondary winding has having N1 fractional portions, which together form a full turn, are in close proximity to the primary winding to establish coupling between the primary winding and the N1 fractional coil portions, the transformer turn ratio from the primary winding to the secondary winding is N2:(N3/N1) where N2 is an integer equal to or greater than 1, N1 is an integer greater than or equal to 2, and N3 is an integer greater than or equal to 1. Also disclosed is a stacked integrated transformer having a primary winding and secondary winding of which one or both have a waterfall structure and a portion of which functions as a ground connected shield between the secondary winding and the primary winding.

公开(公告)号：US09466596B2

公开(公告)日：2016-10-11

申请号：US11964696

申请日：2007-12-26

申请人： Sehat Sutardja ,  Ravishanker Krishnamoorthy

发明人： Sehat Sutardja ,  Ravishanker Krishnamoorthy

IPC分类号： H01L29/66 ,  H01L27/02 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/417

CPC分类号： H01L27/0207 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/41725 ,  H01L29/41758 ,  H01L29/4238 ,  H01L29/78 ,  H01L29/7835

摘要： A Metal Oxide Semiconductor (MOS) device formed on a substrate and a method for forming the MOS device. The MOS device includes a drain region, a gate region surrounding the drain region, source regions arranged around the gate region and across from the drain region, and bulk regions arranged around the gate region and separating the source regions. The gate region is formed in a loop around the drain region. In this manner, the on-resistance (Ron) of a MOS device is decreased without also increasing the area of the MOS device.

摘要翻译： 在基板上形成的金属氧化物半导体（MOS）器件和形成MOS器件的方法。 MOS器件包括漏极区域，围绕漏极区域的栅极区域，围绕栅极区域和漏极区域布置的源极区域以及围绕栅极区域布置并分离源极区域的体区域。 栅极区域围绕漏极区域形成环路。 以这种方式，MOS器件的导通电阻（Ron）减小而不增加MOS器件的面积。

公开(公告)号：US09047765B2

公开(公告)日：2015-06-02

申请号：US11171563

申请日：2005-06-30

申请人： Sehat Sutardja

发明人： Sehat Sutardja

IPC分类号： G06F19/00 ,  G08G1/01 ,  G08G1/0967 ,  G08G1/14 ,  G08G1/00

CPC分类号： G08G1/0104 ,  G08G1/096716 ,  G08G1/096741 ,  G08G1/096758 ,  G08G1/096775 ,  G08G1/096791 ,  G08G1/14 ,  G08G1/20

摘要： A traffic information system for a vehicle comprises a transmitter and a global positioning system (GPS) associated with the vehicle that selectively generates location and vector data. A control module receives the location and vector data and wirelessly transmits the location and vector data using the transmitter when the vehicle is traveling on a first set of predetermined roads and does not transmit the location and vector data when the vehicle is traveling on a second set of predetermined roads.

摘要翻译： 用于车辆的交通信息系统包括与车辆相关联的发射机和全球定位系统（GPS），其选择性地生成位置和矢量数据。 当车辆在第一组预定道路上行驶时，控制模块接收位置和矢量数据并使用发射器无线地发送位置和矢量数据，并且当车辆在第二组上行驶时不传送位置和矢量数据 的预定道路。

公开(公告)号：US08860193B2

公开(公告)日：2014-10-14

申请号：US13153181

申请日：2011-06-03

申请人： Sehat Sutardja ,  Shiann-Ming Liou ,  Huahung Kao

发明人： Sehat Sutardja ,  Shiann-Ming Liou ,  Huahung Kao

IPC分类号： H01L23/495 ,  H01L23/31 ,  H01L21/683 ,  H01L21/56 ,  H01L23/00

CPC分类号： H01L23/49503 ,  H01L21/4825 ,  H01L21/56 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/4952 ,  H01L23/49541 ,  H01L24/03 ,  H01L24/09 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/023 ,  H01L2224/0231 ,  H01L2224/02371 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49433 ,  H01L2224/85424 ,  H01L2224/85447 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： Embodiments of the present disclosure provide an electronic package assembly comprising a solder mask layer, the solder mask layer having at least one opening, and a plurality of pads coupled to the solder mask layer, wherein at least one pad of the plurality of pads includes (i) a first side, (ii) a second side, the first side being disposed opposite to the second side, (iii) a terminal portion and (iv) an extended portion, wherein the first side at the terminal portion is configured to receive a package interconnect structure through the at least one opening in the solder mask layer, the package interconnect structure to route electrical signals between a die and another electronic device that is external to the electronic package assembly, and wherein the second side at the extended portion is configured to receive one or more electrical connections from the die. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例提供了一种电子封装组件，其包括焊料掩模层，焊料掩模层具有至少一个开口，以及耦合到焊料掩模层的多个焊盘，其中多个焊盘中的至少一个焊盘包括 i）第一侧，（ii）第二侧，第一侧与第二侧相对设置，（iii）端子部分和（iv）延伸部分，其中端子部分处的第一侧被配置为接收 通过所述焊料掩模层中的所述至少一个开口的封装互连结构，所述封装互连结构以在管芯与所述电子封装组件外部的另一个电子器件之间布置电信号，并且其中在所述延伸部分处的所述第二侧是 被配置为从所述管芯接收一个或多个电连接。 可以描述和/或要求保护其他实施例。

公开(公告)号：US08847517B2

公开(公告)日：2014-09-30

申请号：US13525711

申请日：2012-06-18

申请人： Sehat Sutardja ,  Pantas Sutardja ,  Wanfeng Zhang ,  Jinho Choi

发明人： Sehat Sutardja ,  Pantas Sutardja ,  Wanfeng Zhang ,  Jinho Choi

IPC分类号： H05B37/02 ,  H05B33/08

CPC分类号： H05B33/0815 ,  H02M3/33507 ,  H05B33/0851

摘要： A system includes a transformer. The transformer includes a first coil and a second coil. The first coil is configured to receive a first voltage based on an output of a switching circuit. The second coil is configured to generate a first current based on the first voltage to power a solid-state load. The system also includes a third coil. The third coil is configured to generate a second voltage based on the first voltage.

摘要翻译： 一个系统包括一个变压器。 变压器包括第一线圈和第二线圈。 第一线圈被配置为基于开关电路的输出接收第一电压。 第二线圈被配置为基于第一电压产生第一电流以对固态负载供电。 该系统还包括第三线圈。 第三线圈被配置为基于第一电压产生第二电压。

公开(公告)号：US08839405B2

公开(公告)日：2014-09-16

申请号：US13571870

申请日：2012-08-10

申请人： Sehat Sutardja ,  Tsahi Daniel ,  Dimitry Melts

发明人： Sehat Sutardja ,  Tsahi Daniel ,  Dimitry Melts

IPC分类号： H04L29/06

CPC分类号： H04L63/02 ,  H04L12/2878 ,  H04L63/105 ,  H04L63/162

摘要： A physical layer device includes memory, a memory control module, and a physical layer module. The memory control module is configured to control access to the memory. The physical layer module is configured to store packets in the memory via the memory control module. The physical layer module includes an interface configured to receive the packets from a network device via a network and an interface bus. The interface bus includes at least one of a control module and a regular expression module. The at least one of the control module and the regular expression module is configured to inspect the packets to determine a security level of the packets. A network interface is configured to, based on the security level, provide the packets to a device separate from the physical layer device.

摘要翻译： 物理层设备包括存储器，存储器控制模块和物理层模块。 存储器控制模块被配置为控制对存储器的访问。 物理层模块被配置为经由存储器控制模块将数据包存储在存储器中。 物理层模块包括经由网络和接口总线从网络设备接收分组的接口。 接口总线包括控制模块和正则表达式模块中的至少一个。 控制模块和正则表达模块中的至少一个被配置为检查分组以确定分组的安全级别。 网络接口被配置为基于安全级别将分组提供给与物理层设备分离的设备。

公开(公告)号：US08802554B2

公开(公告)日：2014-08-12

申请号：US13372315

申请日：2012-02-13

申请人： Sehat Sutardja

发明人： Sehat Sutardja

IPC分类号： H01L21/44 ,  H01L23/485

CPC分类号： H01L23/485 ,  H01L24/05 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/0213 ,  H01L2224/0217 ,  H01L2224/04042 ,  H01L2224/05011 ,  H01L2224/05186 ,  H01L2224/05551 ,  H01L2224/05564 ,  H01L2224/05573 ,  H01L2224/05576 ,  H01L2224/05578 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05686 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48686 ,  H01L2224/48824 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/48886 ,  H01L2224/85035 ,  H01L2224/85365 ,  H01L2924/00014 ,  H01L2924/01327 ,  H01L2924/05442 ,  H01L2924/05042 ,  H01L2924/01029 ,  H01L2924/01014 ,  H01L2924/00 ,  H01L2224/05552

摘要： A method includes forming a pad on an electronic component. The pad comprises conductive material. The method further includes providing passivation material on a surface of the conductive material and removing passivation material from the surface to expose portions of the conductive material to form a bond pad comprising conductive material and passivation material.

摘要翻译： 一种方法包括在电子部件上形成垫。 垫包括导电材料。 该方法还包括在导电材料的表面上提供钝化材料并从表面去除钝化材料以暴露导电材料的部分以形成包含导电材料和钝化材料的接合焊盘。

公开(公告)号：US08717103B2

公开(公告)日：2014-05-06

申请号：US13336857

申请日：2011-12-23

申请人： Poh Boon Leong ,  Ping Song ,  Sehat Sutardja

发明人： Poh Boon Leong ,  Ping Song ,  Sehat Sutardja

IPC分类号： H03F3/04

CPC分类号： H03F3/265 ,  H03F1/223 ,  H03F3/193 ,  H03F3/245 ,  H03F2200/306 ,  H03F2200/408 ,  H03F2200/534 ,  H03F2200/537 ,  H03F2200/541

摘要： An amplifier includes a first transistor, and a first inductor disposed between the first transistor and a voltage source. A first output node is between the first transistor and the first inductor. The amplifier further includes a second inductor disposed between the first transistor and ground. The amplifier further includes a second transistor, and a third inductor disposed between the second transistor and a ground. A second output node is between the second transistor and the third inductor. The amplifier further includes a fourth inductor disposed between the second transistor and the voltage source. The amplifier further includes a first capacitor disposed between the first output node and the second output node, and a second capacitor disposed between a first mid-node, which is between the first transistor and the first inductor, and a second mid-node, which is between the second transistor and fourth inductor.

摘要翻译： 放大器包括第一晶体管和设置在第一晶体管和电压源之间的第一电感器。 第一输出节点位于第一晶体管和第一电感器之间。 放大器还包括设置在第一晶体管和地之间的第二电感器。 放大器还包括第二晶体管，以及设置在第二晶体管和地之间的第三电感器。 第二输出节点在第二晶体管和第三电感之间。 放大器还包括设置在第二晶体管和电压源之间的第四电感器。 所述放大器还包括设置在所述第一输出节点和所述第二输出节点之间的第一电容器，以及设置在所述第一晶体管和所述第一电感器之间的第一中间节点和第二中间节点之间的第二电容器， 在第二晶体管和第四电感之间。