公开(公告)号：US09922824B2

公开(公告)日：2018-03-20

申请号：US14978328

申请日：2015-12-22

申请人： TOKYO ELECTRON LIMITED

发明人： Mitsuhiro Okada

IPC分类号： C23C16/24 ,  H01L21/02 ,  H01L21/67 ,  H01L21/677 ,  H01L21/3205

CPC分类号： H01L21/02532 ,  C23C16/02 ,  C23C16/24 ,  H01L21/02592 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/32055 ,  H01L21/67109 ,  H01L21/67757

摘要： A method of forming a silicon film on a target surface of a target object, including: performing a gas process on the target surface of the target object using an oxygen gas and a hydrogen gas; forming the silicon film on the target surface to which the gas process has been performed, wherein the performing a gas process and the forming the silicon film are performed within a single processing chamber.

公开(公告)号：US20180076239A1

公开(公告)日：2018-03-15

申请号：US15678501

申请日：2017-08-16

申请人： Japan Display Inc.

发明人： Isao SUZUMURA ,  Hajime Watakabe ,  Akihiro Hanada ,  Hirokazu Watanabe

IPC分类号： H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02 ,  H01L29/786

CPC分类号： H01L27/1251 ,  G02F1/134363 ,  G02F1/136227 ,  G02F1/1368 ,  G02F2001/13685 ,  G02F2202/104 ,  H01L21/02532 ,  H01L21/02565 ,  H01L21/02592 ,  H01L21/02675 ,  H01L27/1218 ,  H01L27/1225 ,  H01L27/1229 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/127 ,  H01L27/1274 ,  H01L27/3258 ,  H01L27/3262 ,  H01L27/3276 ,  H01L29/42384 ,  H01L29/66757 ,  H01L29/66969 ,  H01L29/78675 ,  H01L29/78693 ,  H01L2227/323

摘要： The purpose of the present invention is to form both LTPS TFT and Ply-Si TFT on a same substrate. The feature of the display device to realize the above purpose is that: a display device comprising: a substrate including a first TFT having an oxide semiconductor layer and a second TFT having a Poly-Si layer, an undercoat is formed on the substrate, the oxide semiconductor layer is formed on or above the undercoat, a first interlayer insulating film is formed on or above the oxide semiconductor layer, the Poly-Si layer is formed on or above the first interlayer insulating film.

公开(公告)号：US09917019B2

公开(公告)日：2018-03-13

申请号：US14833356

申请日：2015-08-24

申请人： International Business Machines Corporation

发明人： Bruce B. Doris ,  Hong He ,  Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Fee Li Lie ,  Stuart A. Sieg

IPC分类号： H01L29/78 ,  H01L21/84 ,  H01L27/12 ,  H01L27/088 ,  H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L21/306 ,  H01L21/762 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165

CPC分类号： H01L21/845 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/76213 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

摘要： A method for forming a fin on a substrate comprises patterning and etching a layer of a first semiconductor material to define a strained fin, depositing a layer of a second semiconductor material over the fin, the second semiconductor material operative to maintain the a strain in the strained fin, etching to remove a portion of the second semiconductor material to define a cavity that exposes a portion of the fin, etching to remove the exposed portion of the fin such that the fin is divided into a first segment and a second segment, and depositing an insulator material in the cavity, the insulator material contacting the first segment of the fin and the second segment of the fin.

公开(公告)号：US09882006B2

公开(公告)日：2018-01-30

申请号：US15340624

申请日：2016-11-01

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMicroelectronics, Inc.

发明人： Hong He ,  Nicolas Loubet ,  Junli Wang

IPC分类号： H01L29/10 ,  H01L29/161 ,  H01L29/66 ,  H01L21/225 ,  H01L21/311 ,  H01L21/02 ,  H01L29/78 ,  H01L29/167

CPC分类号： H01L29/785 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/2256 ,  H01L21/31116 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/167 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/66818

摘要： A method for channel formation in a fin transistor includes removing a dummy gate and dielectric from a dummy gate structure to expose a region of an underlying fin and depositing an amorphous layer including Ge over the region of the underlying fin. The amorphous layer is oxidized to condense out Ge and diffuse the Ge into the region of the underlying fin to form a channel region with Ge in the fin.

公开(公告)号：US09865619B2

公开(公告)日：2018-01-09

申请号：US14779545

申请日：2015-08-13

申请人： SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.

发明人： Xiaoxiao Wang ,  Peng Du ,  Cong Wang

IPC分类号： H01L27/12 ,  H01L29/786 ,  H01L21/02 ,  H01L21/3213 ,  H01L29/45 ,  H01L29/66 ,  H01L21/22 ,  H01L21/265 ,  G02F1/1368

CPC分类号： H01L27/1222 ,  G02F1/136209 ,  G02F1/1368 ,  G02F2202/104 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/22 ,  H01L21/26513 ,  H01L21/32133 ,  H01L27/1218 ,  H01L27/124 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/458 ,  H01L29/66757 ,  H01L29/786 ,  H01L29/78633 ,  H01L29/78675

摘要： An array substrate and a manufacturing method thereof are provided. The method has steps of: forming a buffer layer, a light-shading layer, and a whole semiconductor layer on a substrate; simultaneously patterning the semiconductor layer and the light-shading layer; and forming a first insulation layer, a first metal layer, a second insulation layer, a second metal layer, a flat layer, and a first transparent conductive layer on the patterned semiconductor layer.

公开(公告)号：US09865435B2

公开(公告)日：2018-01-09

申请号：US15035074

申请日：2015-11-13

申请人： BOE TECHNOLOGY GROUP CO., LTD.

发明人： Xiangjun Tian ,  Seiji Fujino

IPC分类号： H01L21/00 ,  H01J37/32 ,  H01L21/02 ,  C23C16/24 ,  C23C16/50 ,  C23C16/52

CPC分类号： H01J37/32568 ,  C23C16/24 ,  C23C16/50 ,  C23C16/52 ,  H01J37/32357 ,  H01J37/32449 ,  H01J37/32522 ,  H01J37/32541 ,  H01J37/32605 ,  H01J37/32752 ,  H01J2237/3321 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02689 ,  H01L21/02691 ,  H05H1/46 ,  H05H2001/466

摘要： A plasma generator, a plasma annealing device, a deposition crystallization apparatus and a plasma annealing process are disclosed. The plasma generator includes: a gas chamber; a gas intake member configured to introduce a gas into the gas chamber; a cathode and an anode that are configured to apply an electric field to the gas introduced into the gas chamber to ionize the gas into plasma; a cooling water circulation member configured to control a temperature of the plasma generator; and a plasma beam outlet disposed on a top face of the gas chamber. The plasma annealing device including the plasma generator can generate a plasma beam, which can be used in annealing to amorphous silicon and crystallize the amorphous silicon to polycrystalline silicon.

公开(公告)号：US20180006157A1

公开(公告)日：2018-01-04

申请号：US15635989

申请日：2017-06-28

申请人： AU OPTRONICS CORPORATION

发明人： Jia-Hong YE

IPC分类号： H01L29/786 ,  H01L21/02 ,  H01L29/24 ,  H01L29/66 ,  H01L29/423

CPC分类号： H01L29/7869 ,  H01L21/02178 ,  H01L21/02244 ,  H01L21/02422 ,  H01L21/02425 ,  H01L21/02488 ,  H01L21/02565 ,  H01L21/02592 ,  H01L21/02667 ,  H01L21/02672 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/24 ,  H01L29/42356 ,  H01L29/66969 ,  H01L29/78696

摘要： The present invention provides two methods for crystallizing a metal oxide semiconductor layer and a semiconductor structure. The first crystallization method is treating an amorphous metal oxide semiconductor layer including indium with oxygen at a pressure of about 550 mtorr to about 5000 mtorr and at a temperature of about 200° C. to about 750° C. The second crystallization method is, firstly, sequentially forming a first amorphous metal oxide semiconductor layer, an aluminum layer, and a second amorphous metal oxide semiconductor layer on a substrate, and, secondly, treating the first amorphous metal oxide semiconductor layer, the aluminum layer, and the second amorphous metal oxide semiconductor layer with an inert gas at a temperature of about 350° C. to about 650° C.

公开(公告)号：US20170373086A1

公开(公告)日：2017-12-28

申请号：US15190574

申请日：2016-06-23

申请人： SanDisk Technologies LLC

发明人： Liang Pang ,  Jayavel Pachamuthu ,  Yingda Dong

IPC分类号： H01L27/11582 ,  H01L27/11568 ,  H01L21/28 ,  H01L21/02 ,  H01L29/66 ,  H01L21/311

CPC分类号： H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02238 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/02667 ,  H01L21/28282 ,  H01L21/31111 ,  H01L27/11568 ,  H01L29/42368 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/7827 ,  H01L29/7926

摘要： Techniques for fabricating a memory device which has reduced neighboring word line interference, and a corresponding memory device. The memory device comprises a stack of alternating conductive and dielectric layers, where the conductive layers form word lines or control gates of memory cells. In one aspect, rounding off of the control gate layers due to inadvertent oxidation during fabrication is avoided. An amorphous silicon layer is deposited along the sidewall of the memory holes, adjacent to the control gate layers. Si3N4 is deposited along the amorphous silicon layer and oxidized in the memory hole to form SiO2. The amorphous silicon layer acts as an oxidation barrier for the sacrificial material of the control gate layers. The amorphous silicon layer is subsequently oxidized to also form SiO2. The two SiO2 layers together form a blocking oxide layer.

公开(公告)号：US20170372969A1

公开(公告)日：2017-12-28

申请号：US15261302

申请日：2016-09-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kuo-Cheng Ching ,  Shi Ning Ju ,  Chih-Hao Wang ,  Ying-Keung Leung ,  Carlos H. Diaz

IPC分类号： H01L21/8234 ,  H01L21/762 ,  H01L21/02 ,  H01L29/78

CPC分类号： H01L21/823431 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02247 ,  H01L21/02271 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02634 ,  H01L21/76237 ,  H01L21/823481 ,  H01L29/7851

摘要： A FinFET includes a semiconductor layer having a fin structure that protrudes out of the semiconductor layer. The fin structure includes a first segment and a second segment disposed over the first segment. A dielectric layer is disposed over the semiconductor layer. The first segment of the fin structure is surrounded by the dielectric layer. A metal layer is disposed over the dielectric layer. The second segment of the fin structure is surrounded by the metal layer. The dielectric layer has a greater nitrogen content than the metal layer. The first segment of the fin structure also has a first side surface that is rougher than a second side surface of the second segment of the fin structure.

公开(公告)号：US09852904B2

公开(公告)日：2017-12-26

申请号：US14813413

申请日：2015-07-30

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Shunpei Yamazaki ,  Hideomi Suzawa ,  Shinya Sasagawa ,  Tetsuhiro Tanaka

IPC分类号： H01L21/441 ,  H01L21/4757 ,  H01L21/4763 ,  H01L29/66 ,  H01L29/45 ,  H01L29/786 ,  H01L21/02 ,  H01L29/04 ,  H01L29/26 ,  H01L29/78 ,  C23C14/08 ,  C23C14/34 ,  H01L29/49

CPC分类号： H01L21/02565 ,  C23C14/086 ,  C23C14/3414 ,  H01L21/02488 ,  H01L21/02554 ,  H01L21/02592 ,  H01L21/02609 ,  H01L21/02617 ,  H01L21/02631 ,  H01L21/441 ,  H01L21/47576 ,  H01L21/47635 ,  H01L29/045 ,  H01L29/26 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78 ,  H01L29/7869

摘要： In a semiconductor device in which a channel formation region is included in an oxide semiconductor layer, an oxide insulating film below and in contact with the oxide semiconductor layer and a gate insulating film over and in contact with the oxide semiconductor layer are used to supply oxygen of the gate insulating film, which is introduced by an ion implantation method, to the oxide semiconductor layer.