公开(公告)号：US12165705B2

公开(公告)日：2024-12-10

申请号：US18362863

申请日：2023-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chin-I Su ,  Chung-Cheng Chou ,  Yu-Der Chih ,  Zheng-Jun Lin

IPC: G11C13/00

Abstract: A method of operating a memory circuit includes generating a first current in response to a first voltage. The first current includes a first set of leakage currents and a first write current. The method further includes generating, by a tracking circuit, a second set of leakage currents configured to track the first set of leakage currents of the first column of memory cells, and mirroring the first current in a first path with a second current in a second path by a first current mirror. The second current includes the second set of leakage currents and a second write current. The first write current corresponds to the second write current. The first set of leakage currents corresponds to the second set of leakage currents.

公开(公告)号：US12073916B2

公开(公告)日：2024-08-27

申请号：US18138305

申请日：2023-04-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Der Chih

IPC: G06F11/00 ,  G06F1/30 ,  G06F11/14 ,  G06F11/30 ,  G11C5/14 ,  G11C7/20 ,  G11C11/4072

CPC classification number: G11C7/20 ,  G06F1/30 ,  G06F11/1469 ,  G06F11/3037 ,  G06F11/3058 ,  G11C5/148 ,  G11C11/4072

Abstract: A system includes: a processor; a register configured to store a plurality of words, non-volatile memory having a plurality of cells, each cell corresponding to one of the words of the register, and wherein the each cell of the plurality of cells are set to an initial reset value; a first controller that in response to a loss in power: determines the word stored by the register; and changes the initial reset value of the cell of the non-volatile memory corresponding to the determined word stored by the register to a set value; a second controller that in response to detecting a restoration in power: identifies the cell having the set value; writes the word corresponding to the identified cell to the register; and resets the cells of the non-volatile memory to the initial reset value.

公开(公告)号：US12041860B2

公开(公告)日：2024-07-16

申请号：US17581153

申请日：2022-01-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yu-Der Chih ,  Wen-Zhang Lin ,  Yun-Sheng Chen ,  Jonathan Tsung-Yung Chang ,  Chrong-Jung Lin ,  Ya-Chin King ,  Cheng-Jun Lin ,  Wang-Yi Lee

IPC: H10N70/00 ,  H10B63/00

CPC classification number: H10N70/021 ,  H10B63/80 ,  H10N70/063 ,  H10N70/066 ,  H10N70/068 ,  H10N70/841

Abstract: A resistive memory device includes a bottom electrode, a top electrode and a resistance changing element. The top electrode is disposed above and spaced apart from the bottom electrode, and has a downward protrusion aligned with the bottom electrode. The resistance changing element covers side and bottom surfaces of the downward protrusion.

公开(公告)号：US12009029B2

公开(公告)日：2024-06-11

申请号：US18185312

申请日：2023-03-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yu-Der Chih ,  Meng-Fan Chang ,  May-Be Chen ,  Cheng-Xin Xue ,  Je-Syu Liu

IPC: G11C8/00 ,  G06F7/544 ,  G11C7/06 ,  G11C7/10 ,  G11C7/14 ,  G11C13/00

CPC classification number: G11C13/004 ,  G06F7/5443 ,  G11C7/06 ,  G11C7/1051 ,  G11C7/1063 ,  G11C7/14 ,  G11C13/0069 ,  G11C2013/0054

Abstract: A system is provided. The system includes a multiply-and-accumulate circuit and a local generator. The multiply-and-accumulate circuit is coupled to a memory array and generates a multiply-and-accumulate signal indicating a computational output of the memory array. The local generator is coupled to the memory array and generates at least one reference signal at a node in response to one of a plurality of global signals that are generated according to a number of the computational output. The local generator is further configured to generate an output signal according to the signal and a summation of the at least one reference signal at the node.

公开(公告)号：US11978518B2

公开(公告)日：2024-05-07

申请号：US17585031

申请日：2022-01-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Chieh Chen ,  Cheng-Hsiung Kuo ,  Yu-Der Chih

IPC: G11C16/28 ,  G11C16/10 ,  H03K19/20

CPC classification number: G11C16/28 ,  G11C16/10 ,  H03K19/20

Abstract: A sense amplifier control system includes a precharge control switch configured to receive a precharge signal. A reference cell is configured to receive a reference word line signal. In a precharge phase, the control switch is controlled in response to the precharge signal to precharge the reference input node to a predetermined precharge level. In a sensing phase subsequent to the pre-charge phase, the trigger circuit is configured to output a triggering signal at the output terminal in response to the reference input node reaching a triggering level.

公开(公告)号：US11961546B2

公开(公告)日：2024-04-16

申请号：US17391639

申请日：2021-08-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Fu Lee ,  Hon-Jarn Lin ,  Po-Hao Lee ,  Ku-Feng Lin ,  Yi-Chun Shih ,  Yu-Der Chih

IPC: G11C11/06 ,  G11C11/08 ,  G11C11/16 ,  H10B61/00 ,  H10N50/10

CPC classification number: G11C11/1675 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1673 ,  H10B61/22 ,  H10N50/10

Abstract: A reference circuit for generating a reference current includes a plurality of resistive elements including at least one magnetic tunnel junction (MTJ). A control circuit is coupled to a first terminal of the at least one MTJ and is configured to selectively flow current through the at least one MTJ in the forward and inverse direction to generate a reference current.

公开(公告)号：US11943936B2

公开(公告)日：2024-03-26

申请号：US17400615

申请日：2021-08-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Yu-Der Chih ,  May-Be Chen ,  Yun-Sheng Chen ,  Jonathan Tsung-Yung Chang ,  Wen Zhang Lin ,  Chrong Jung Lin ,  Ya-Chin King ,  Chieh Lee ,  Wang-Yi Lee

IPC: H10B63/00 ,  H01L29/40 ,  H01L29/78

CPC classification number: H10B63/30 ,  H01L29/401 ,  H01L29/785

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a first transistor, a first resistive random access memory (RRAM) resistor, and a second RRAM resistor. The first resistor includes a first resistive material layer, a first electrode shared by the second resistor, and a second electrode. The second resistor includes the first electrode, a second resistive material layer, and a third electrode. The first electrode is electrically coupled to the first transistor.

公开(公告)号：US11923036B2

公开(公告)日：2024-03-05

申请号：US18168226

申请日：2023-02-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yi-Chun Shih ,  Chia-Fu Lee ,  Yu-Der Chih

IPC: G11C7/08 ,  G11C7/06 ,  G11C7/10 ,  G11C11/16 ,  G11C29/42

CPC classification number: G11C7/08 ,  G11C7/067 ,  G11C7/1039 ,  G11C11/1673 ,  G11C29/42

Abstract: A memory device, such as an MRAM memory, includes a memory array with a plurality of bit cells. The memory array is configured to store trimming information and store user data. A sense amplifier is configured to read the trimming information from the memory array, and a trimming register is configured to receive the trimming information from the sense amplifier. The sense amplifier is configured to receive the trimming information from the trimming register so as to operate in a trimmed mode for reading the user data from the memory array.

公开(公告)号：US11783870B2

公开(公告)日：2023-10-10

申请号：US17843786

申请日：2022-06-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Fu Lee ,  Hon-Jarn Lin ,  Yu-Der Chih

IPC: G11C7/02 ,  G11C7/06

CPC classification number: G11C7/062 ,  G11C2207/063

Abstract: A sense amplifier is provided. A first terminal of a first invertor is connected to a power node and a second terminal of the first invertor is connected to a cell current source. A first terminal of a second invertor is connected to the power node and a second terminal of the second invertor is connected to a reference current source. The first invertor is cross coupled with the second invertor at a first node and a second node. A pre-charge circuit is connected to the first node and the second node. A first pull up transistor and a second pull up transistor are connected between a supply voltage node and the power node. A signal level detector circuit is connected to the second pull up transistor. The signal level detector circuit switches on the second pull up transistor when a remaining voltage on one of the first node and the second node is below a reference voltage.

公开(公告)号：US20230273752A1

公开(公告)日：2023-08-31

申请号：US18313374

申请日：2023-05-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hiroki Noguchi ,  Shih-Lien Linus Lu ,  Yu-Der Chih ,  Yih Wang

IPC: G06F3/06 ,  G06F9/48 ,  G06F1/28

CPC classification number: G06F3/0659 ,  G06F1/28 ,  G06F3/0604 ,  G06F3/0673 ,  G06F9/4893

Abstract: A memory device including a memory array with a plurality of memory macros, a power supplying circuit, and a controller is provided. The power supplying circuit is coupled to the memory array. The controller is coupled to the memory array. The power supplying circuit is configured to provide power to perform write operations to a number of the memory macros at the same time. The number of the memory macros for the write operations performed at the same time is not higher than a maximum number of the memory macros. The controller obtains the maximum number of the memory macros for the write operations performed at the same time by the power supplying circuit. The controller re-arranges a schedule for a sequence of the write operations of the memory macros to generate a re-arranged schedule. The maximum number is taken as a threshold value. In the re-arranged schedule, a number of part of the memory macros for the write operations performed at the same time is equal to or less then the threshold value.