公开(公告)号：US20240347090A1

公开(公告)日：2024-10-17

申请号：US18635929

申请日：2024-04-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Fu Lee ,  Hon-Jarn Lin ,  Po-Hao Lee ,  Ku-Feng Lin ,  Yi-Chun Shih ,  Yu-Der Chih

IPC: G11C11/16 ,  H10B61/00 ,  H10N50/10

CPC classification number: G11C11/1675 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1673 ,  H10B61/22 ,  H10N50/10

Abstract: A reference circuit for generating a reference current includes a plurality of resistive elements including at least one magnetic tunnel junction (MTJ). A control circuit is coupled to a first terminal of the at least one MTJ and is configured to selectively flow current through the at least one MTJ in the forward and inverse direction to generate a reference current.

公开(公告)号：US11641193B2

公开(公告)日：2023-05-02

申请号：US17815322

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Fu Lee ,  Hon-Jarn Lin ,  Yu-Der Chih

IPC: H03K3/356

Abstract: A circuit includes cross coupled invertors including a first invertor and a second inventor. The first invertor and the second invertor are cross coupled at a first data node and a second data node. An input unit is coupled between the cross-coupled invertors and a power node. The input unit controls the cross-coupled invertors in response to a first input signal received at a first input terminal of the input unit and a second input signal received at a second input terminal of the input unit. A first transistor is connected between the power node and a supply node. The first transistor connects the power node to the supply node in response to an enable signal changing to a first value. A second transistor is connected between the power node and ground. The second transistor connects the power node to the ground in response to the enable signal changing to a second value.

公开(公告)号：US11081155B2

公开(公告)日：2021-08-03

申请号：US16431158

申请日：2019-06-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Fu Lee ,  Hon-Jarn Lin ,  Po-Hao Lee ,  Ku-Feng Lin ,  Yi-Chun Shih ,  Yu-Der Chih

IPC: G11C11/16 ,  H01L43/08 ,  H01L27/22

Abstract: A reference circuit for generating a reference current includes a plurality of resistive elements including at least one magnetic tunnel junction (MTJ). A control circuit is coupled to a first terminal of the at least one MTJ and is configured to selectively flow current through the at least one MTJ in the forward and inverse direction to generate a reference current.

公开(公告)号：US11961546B2

公开(公告)日：2024-04-16

申请号：US17391639

申请日：2021-08-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Fu Lee ,  Hon-Jarn Lin ,  Po-Hao Lee ,  Ku-Feng Lin ,  Yi-Chun Shih ,  Yu-Der Chih

IPC: G11C11/06 ,  G11C11/08 ,  G11C11/16 ,  H10B61/00 ,  H10N50/10

CPC classification number: G11C11/1675 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1673 ,  H10B61/22 ,  H10N50/10

Abstract: A reference circuit for generating a reference current includes a plurality of resistive elements including at least one magnetic tunnel junction (MTJ). A control circuit is coupled to a first terminal of the at least one MTJ and is configured to selectively flow current through the at least one MTJ in the forward and inverse direction to generate a reference current.

公开(公告)号：US11783870B2

公开(公告)日：2023-10-10

申请号：US17843786

申请日：2022-06-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Fu Lee ,  Hon-Jarn Lin ,  Yu-Der Chih

IPC: G11C7/02 ,  G11C7/06

CPC classification number: G11C7/062 ,  G11C2207/063

Abstract: A sense amplifier is provided. A first terminal of a first invertor is connected to a power node and a second terminal of the first invertor is connected to a cell current source. A first terminal of a second invertor is connected to the power node and a second terminal of the second invertor is connected to a reference current source. The first invertor is cross coupled with the second invertor at a first node and a second node. A pre-charge circuit is connected to the first node and the second node. A first pull up transistor and a second pull up transistor are connected between a supply voltage node and the power node. A signal level detector circuit is connected to the second pull up transistor. The signal level detector circuit switches on the second pull up transistor when a remaining voltage on one of the first node and the second node is below a reference voltage.

公开(公告)号：US12165732B2

公开(公告)日：2024-12-10

申请号：US18447872

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Fu Lee ,  Hon-Jarn Lin ,  Yu-Der Chih

IPC: G11C7/02 ,  G11C7/06

Abstract: A sense amplifier is provided. A first terminal of a first invertor is connected to a power node and a second terminal of the first invertor is connected to a cell current source. A first terminal of a second invertor is connected to the power node and a second terminal of the second invertor is connected to a reference current source. The first invertor is cross coupled with the second invertor at a first node and a second node. A pre-charge circuit is connected to the first node and the second node. A first pull up transistor and a second pull up transistor are connected between a supply voltage node and the power node. A signal level detector circuit is connected to the second pull up transistor. The signal level detector circuit switches on the second pull up transistor when a remaining voltage on one of the first node and the second node is below a reference voltage.

公开(公告)号：US20240046968A1

公开(公告)日：2024-02-08

申请号：US18447872

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Fu Lee ,  Hon-Jarn Lin ,  Yu-Der Chih

IPC: G11C7/06

CPC classification number: G11C7/062 ,  G11C2207/063

Abstract: A sense amplifier is provided. A first terminal of a first invertor is connected to a power node and a second terminal of the first invertor is connected to a cell current source. A first terminal of a second invertor is connected to the power node and a second terminal of the second invertor is connected to a reference current source. The first invertor is cross coupled with the second invertor at a first node and a second node. A pre-charge circuit is connected to the first node and the second node. A first pull up transistor and a second pull up transistor are connected between a supply voltage node and the power node. A signal level detector circuit is connected to the second pull up transistor. The signal level detector circuit switches on the second pull up transistor when a remaining voltage on one of the first node and the second node is below a reference voltage.

公开(公告)号：US20220360254A1

公开(公告)日：2022-11-10

申请号：US17815322

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Fu Lee ,  Hon-Jarn Lin ,  Yu-Der Chih

IPC: H03K3/356

Abstract: A circuit includes cross coupled invertors including a first invertor and a second inventor. The first invertor and the second invertor are cross coupled at a first data node and a second data node. An input unit is coupled between the cross-coupled invertors and a power node. The input unit controls the cross-coupled invertors in response to a first input signal received at a first input terminal of the input unit and a second input signal received at a second input terminal of the input unit. A first transistor is connected between the power node and a supply node. The first transistor connects the power node to the supply node in response to an enable signal changing to a first value. A second transistor is connected between the power node and ground. The second transistor connects the power node to the ground in response to the enable signal changing to a second value.

公开(公告)号：US20220319558A1

公开(公告)日：2022-10-06

申请号：US17843786

申请日：2022-06-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Fu Lee ,  Hon-Jarn Lin ,  Yu-Der Chih

IPC: G11C7/06

Abstract: A sense amplifier is provided. A first terminal of a first invertor is connected to a power node and a second terminal of the first invertor is connected to a cell current source. A first terminal of a second invertor is connected to the power node and a second terminal of the second invertor is connected to a reference current source. The first invertor is cross coupled with the second invertor at a first node and a second node. A pre-charge circuit is connected to the first node and the second node. A first pull up transistor and a second pull up transistor are connected between a supply voltage node and the power node. A signal level detector circuit is connected to the second pull up transistor. The signal level detector circuit switches on the second pull up transistor when a remaining voltage on one of the first node and the second node is below a reference voltage.

公开(公告)号：US11973502B2

公开(公告)日：2024-04-30

申请号：US18310143

申请日：2023-05-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Fu Lee ,  Hon-Jarn Lin ,  Yu-Der Chih

IPC: H03K3/356

CPC classification number: H03K3/35613

Abstract: A circuit includes cross coupled invertors including a first invertor and a second inventor. The first invertor and the second invertor are cross coupled at a first data node and a second data node. An input unit is coupled between the cross-coupled invertors and a power node. The input unit controls the cross-coupled invertors in response to a first input signal received at a first input terminal of the input unit and a second input signal received at a second input terminal of the input unit. A first transistor is connected between the power node and a supply node. The first transistor connects the power node to the supply node in response to an enable signal changing to a first value. A second transistor is connected between the power node and ground. The second transistor connects the power node to the ground in response to the enable signal changing to a second value.