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    RRAM circuit
    2.
    发明授权
    RRAM circuit 有权

    公开(公告)号：US11942150B2

    公开(公告)日：2024-03-26

    申请号：US18054359

    申请日：2022-11-10

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Chung-Cheng Chou ,  Zheng-Jun Lin ,  Pei-Ling Tseng

    IPC: G11C11/00 ,  G11C13/00

    CPC classification number: G11C13/0038 ,  G11C13/003 ,  G11C2213/15 ,  G11C2213/79

    Abstract: A resistive random-access memory (RRAM) circuit includes an RRAM device configured to output a cell current responsive to a bit line voltage, and a current limiter including an input terminal coupled to the RRAM device, first and second parallel current paths configured to conduct the cell current between the input terminal and a reference voltage node, and an amplifier configured to generate a first signal responsive to a voltage level at the input terminal and a reference voltage level. Each of the first and second current paths includes a switching device configured to selectively conduct a portion of the cell current responsive to the first signal.

    DYNAMIC INHIBIT VOLTAGE TO REDUCE WRITE POWER FOR RANDOM-ACCESS MEMORY
    4.
    发明申请
    DYNAMIC INHIBIT VOLTAGE TO REDUCE WRITE POWER FOR RANDOM-ACCESS MEMORY 有权

    公开(公告)号：US20220254412A1

    公开(公告)日：2022-08-11

    申请号：US17470849

    申请日：2021-09-09

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Zheng-Jun Lin ,  Chin-I Su ,  Pei-Ling Tseng ,  Chung-Cheng Chou

    IPC: G11C13/00

    Abstract: In some aspects of the present disclosure, a memory device is disclosed. In some aspects, the memory device includes a first voltage regulator to receive a word line voltage provided to a memory array; a resistor network coupled to the first voltage regulator to provide an inhibit voltage to the memory array, wherein the resistor network comprises a plurality of resistors and wherein each of the resistors are coupled in series to an adjacent one of the plurality of resistors; and a switch network comprising a plurality of switches, wherein each of the switches are coupled to a corresponding one of the plurality of resistors and to the memory array via a second voltage regulator.

    LOW-DROPOUT (LDO) REGULATOR
    5.
    发明申请
    LOW-DROPOUT (LDO) REGULATOR 有权

    公开(公告)号：US20210096586A1

    公开(公告)日：2021-04-01

    申请号：US17010064

    申请日：2020-09-02

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Zheng-Jun Lin ,  Chung-Cheng Chou ,  Yu-Der Chih ,  Chin-I Su

    IPC: G05F1/575 ,  G05F1/46 ,  H02M3/155

    Abstract: A voltage regulator circuit is provided. The voltage regulator circuit includes a voltage regulator configured to provide an output voltage at an output terminal. A plurality of macros are connectable at a plurality of connection nodes of a connector connected to the output terminal of the voltage regulator. A feedback circuit having a plurality of feedback loops is connectable to the plurality of connection nodes. The feedback loop of the plurality of feedback loops, when connected to a connection node of the plurality of connection nodes, is configured to provide an instantaneous voltage of the connection node as a feedback to the voltage regulator. The voltage regulator is configured, in response to the instantaneous voltage, regulate the output voltage to maintain the instantaneous voltage of the connection node approximately equal to a reference voltage.

    LOW-DROPOUT (LDO) REGULATOR WITH A FEEDBACK CIRCUIT
    7.
    发明公开
    LOW-DROPOUT (LDO) REGULATOR WITH A FEEDBACK CIRCUIT 审中-公开

    公开(公告)号：US20240036597A1

    公开(公告)日：2024-02-01

    申请号：US17877115

    申请日：2022-07-29

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Zheng-Jun Lin ,  Chung-Cheng Chou ,  Yu-Der Chih ,  Chin-I Su

    IPC: G05F1/575 ,  G05F1/565

    CPC classification number: G05F1/575 ,  G05F1/565

    Abstract: A voltage regulator circuit is provided. The voltage regulator circuit includes a voltage regulator configured to provide an output voltage at an output terminal. A plurality of macros are connectable at a plurality of connection nodes of a connector connected to the output terminal of the voltage regulator. A feedback circuit having a plurality of feedback loops is connectable to the plurality of connection nodes. The feedback loop of the plurality of feedback loops, when connected to a connection node of the plurality of connection nodes, is configured to provide an instantaneous voltage of the connection node as a feedback to the voltage regulator. The voltage regulator is configured, in response to the instantaneous voltage, regulate the output voltage to maintain the instantaneous voltage of the connection node approximately equal to a reference voltage.

    Memory cell array circuit and method of forming the same
    8.
    发明授权
    Memory cell array circuit and method of forming the same 有权

    公开(公告)号：US11735263B2

    公开(公告)日：2023-08-22

    申请号：US17871144

    申请日：2022-07-22

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Chin-I Su ,  Chung-Cheng Chou ,  Yu-Der Chih ,  Zheng-Jun Lin

    IPC: G11C13/00

    CPC classification number: G11C13/0069 ,  G11C13/0028 ,  G11C13/0038 ,  G11C2013/0078 ,  G11C2213/79

    Abstract: A method of operating a memory circuit includes generating a first voltage by a first amplifier circuit of a first driver circuit coupled to a first column of memory cells, and generating a first current in response to the first voltage. The first current includes a first set of leakage currents and a first write current. The method further includes generating, by a tracking circuit, a second set of leakage currents configured to track the first set of leakage currents of the first column of memory cells, and mirroring the first current in a first path with a second current in a second path by a first current mirror. The second current includes the second set of leakage currents and a second write current. The first write current corresponds to the second write current. The first set of leakage currents corresponds to the second set of leakage currents.

    Semicoductor device and operation method thereof
    9.
    发明授权
    Semicoductor device and operation method thereof 有权

    公开(公告)号：US11609815B1

    公开(公告)日：2023-03-21

    申请号：US17461532

    申请日：2021-08-30

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Zheng-Jun Lin ,  Pei-Ling Tseng ,  Hsueh-Chih Yang ,  Chung-Cheng Chou ,  Yu-Der Chih

    IPC: G06F11/10 ,  G11C7/10 ,  H03K19/20

    Abstract: A semiconductor device includes a memory circuit, an error correction code circuit, a register circuit and a write circuit. The memory circuit is configured to output, in response to at least one address signal, first data associated with at least one memory cell in the memory circuit. The error correction code circuit is configured to convert the first data to second data and configured to generate error information when the first data is not identical to the second data. The register circuit is configured to output, based on the error information, reset information corresponding to the at least one address signal. The write circuit is configured to reset the at least one memory cell according to the reset information. A method is also disclosed herein.

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