公开(公告)号：US10333007B2

公开(公告)日：2019-06-25

申请号：US15686827

申请日：2017-08-25

Applicant: QUALCOMM Incorporated

Inventor： Ye Lu ,  Yun Yue ,  Chuan-Hsing Chen ,  Bin Yang ,  Lixin Ge ,  Ken Liao

IPC: H01L29/93 ,  H01L29/66 ,  H01L29/423 ,  H01L29/45 ,  H01L23/482 ,  H01L23/485 ,  H01L23/66

Abstract: A short-channel metal oxide semiconductor varactor may include a source region of a first polarity having a source via contact. The varactor may further include a drain region of the first polarity having a drain via contact. The varactor may further include a channel region of the first polarity between the source region and the drain region. The channel region may include a gate. The varactor may further include at least one self-aligned contact (SAC) on the gate and between the source via contact and the drain via contact.

公开(公告)号：US11487507B2

公开(公告)日：2022-11-01

申请号：US16868202

申请日：2020-05-06

Applicant: QUALCOMM Incorporated

Inventor： Ye Lu ,  Zhongze Wang ,  Periannan Chidambaram

IPC: G06F7/523 ,  G11C11/412 ,  G11C11/419 ,  G06N3/063

Abstract: A bit cell circuit of a most-significant bit (MSB) of a multi-bit product generated in an array of bit cells in a compute-in-memory (CIM) array circuit is configured to receive a higher supply voltage than a supply voltage provided to a bit cell circuit of another bit cell corresponding to another bit of the multi-bit product. A bit cell circuit receiving a higher supply voltage increases a voltage difference between increments of an accumulated voltage, which can increase accuracy of an analog-to-digital converter determining a pop-count. A bit cell circuit of the MSB in the CIM array circuit receives the higher supply voltage to increase accuracy of the MSB which increases accuracy of the CIM array circuit output. A capacitance of a capacitor in the bit cell circuit of the MSB is smaller to avoid an increase in energy consumption due to the higher voltage.

公开(公告)号：US11302773B2

公开(公告)日：2022-04-12

申请号：US16155694

申请日：2018-10-09

Applicant: QUALCOMM Incorporated

Inventor： Ye Lu ,  Junjing Bao ,  Haitao Cheng ,  Chao Song

IPC: H01L49/02 ,  H01L23/522 ,  H01L23/532

Abstract: A low cost capacitor (e.g., metal-insulator-metal (MIM) capacitor) is included in the back-end-of-line layers for effective routing and area savings. The capacitor has a first electrode (e.g., a first terminal of the capacitor) including a conductive back-end-of-line (BEOL) layer and a second electrode (e.g., a second terminal of the capacitor) including a nitride-based metal. The capacitor also has an etch stop layer (e.g., a dielectric of the capacitor) between the first electrode and the second electrode.

公开(公告)号：US10964356B2

公开(公告)日：2021-03-30

申请号：US16706429

申请日：2019-12-06

Applicant: QUALCOMM Incorporated

Inventor： Zhongze Wang ,  Xia Li ,  Ye Lu ,  Yandong Gao

IPC: G11C7/10 ,  G11C7/06 ,  G06N3/06 ,  G11C11/4094 ,  G11C11/419 ,  G11C11/4074

Abstract: A charge sharing Compute In Memory (CIM) may comprise an XNOR bit cell with an internal capacitor between the XNOR output node and a system voltage. Alternatively, a charge sharing CIM may comprise an XNOR bit cell with an internal capacitor between the XNOR output node and a read bit line. Alternatively, a charge sharing CIM may comprise an XNOR bit cell with an internal cap between XNOR and read bit line with a separate write bit line and write bit line bar.

公开(公告)号：US20200152739A1

公开(公告)日：2020-05-14

申请号：US16189855

申请日：2018-11-13

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Xia Li ,  Gengming Tao ,  Ye Lu

IPC: H01L29/08 ,  H01L29/24 ,  H01L29/10 ,  H01L29/51 ,  H01L29/78 ,  H01L21/768 ,  H01L21/02

Abstract: A transistor comprises a substrate, a first buffer layer on the substrate, a source region, a drain region, and a channel region on the first buffer layer, a gate on the channel region, a source contact, and a drain contact. The source contact is configured to contact at least three sides of the source region and the drain contact is configured to contact at least three sides of the drain region to lower contact resistance in the source region and in the drain region.

公开(公告)号：US20200066829A1

公开(公告)日：2020-02-27

申请号：US16106160

申请日：2018-08-21

Applicant: Qualcomm Incorporated

Inventor： Haitao CHENG ,  Chao Song ,  Ye Lu

IPC: H01L49/02 ,  H01F17/00 ,  H01L23/522 ,  H01L27/08

Abstract: Aspects generally relate to adjusting, or lowering, the Q of an inductor. In one embodiment, an integrated circuit includes an inductor and a conductive closed ring inside a periphery of the inductor. In another embodiment, there can be a plurality of closed rings inside the periphery of the inductor. The conductive closed rings are magnetically coupled to the inductor to adjust the Q.

公开(公告)号：US20190326057A1

公开(公告)日：2019-10-24

申请号：US15961594

申请日：2018-04-24

Applicant: QUALCOMM Incorporated

Inventor： Ye Lu ,  Haitao Cheng ,  Chao Song

IPC: H01G4/10 ,  H01G4/01 ,  H01L23/522

Abstract: Methods, systems, and devices for a finger metal-on-metal (FMOM) capacitor including a negative capacitance material are described. In one examples, a FMOM capacitor may include a first electrode and a second electrode. The FMOM capacitor may include a dielectric layer coating a first sidewall of the first electrode and a second sidewall of a second electrode. A portion of the first sidewall may be substantially parallel to a portion of the second sidewall. The FMOM capacitor may also include a negative capacitance material disposed in a channel between the first sidewall of the first electrode and the second sidewall of the second electrode. The negative capacitance material may extend in a direction that is substantially parallel to the portion of the first sidewall and the portion of the second sidewall.

公开(公告)号：US10431540B1

公开(公告)日：2019-10-01

申请号：US16039213

申请日：2018-07-18

Applicant: QUALCOMM Incorporated

Inventor： Haitao Cheng ,  Chao Song ,  Ye Lu

IPC: H01L21/02 ,  H01L23/522 ,  H03F3/195 ,  H01L49/02 ,  H01L23/66

Abstract: A semiconductor device reduces parasitic capacitance between a metal-oxide-metal (MOM)/metal-insulator-metal (MIM) capacitors and a semiconductor substrate. The semiconductor device includes the semiconductor substrate (e.g., a silicon substrate, a III-V compound semiconductor substrate, or a silicon on insulator (SOI) substrate), a magnetic material layer, and a capacitor. The magnetic material layer is between the semiconductor substrate and the capacitor.

公开(公告)号：US20190181137A1

公开(公告)日：2019-06-13

申请号：US15835810

申请日：2017-12-08

Applicant: QUALCOMM Incorporated

Inventor： Ye Lu ,  Bin Yang ,  Lixin Ge

IPC: H01L27/06 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/088 ,  H03K19/0185 ,  G06F17/50 ,  H01L21/762

Abstract: An integrated circuit may include a substrate, a first three-dimensional (3D) transistor formed on a first diffusion region of the substrate, and a second 3D transistor formed on a second diffusion region of the substrate. The first 3D transistor may include a gate that extends from between a source and a drain of the first 3D transistor, across an isolation region of the substrate, to and between a source and a drain of the second 3D transistor. The gate may include a gate metal that has an isolation portion extending over the isolation region of the substrate and a diffusion portion extending over the first and second diffusion regions of the substrate. The isolation portion of the gate metal has a thickness less than a maximum thickness of the diffusion portion of the gate metal.

公开(公告)号：US10312891B1

公开(公告)日：2019-06-04

申请号：US16142476

申请日：2018-09-26

Applicant: QUALCOMM Incorporated

Inventor： Chao Song ,  Zhengzheng Wu ,  Haitao Cheng ,  Ye Lu

IPC: H03K5/00 ,  H01L49/02 ,  H01L27/06 ,  H03K19/20

Abstract: In certain aspects, an integrated circuit comprises a signal path having a path delay from an input to an output, wherein the signal path comprises a path capacitor having a path capacitance. The integrated circuit also comprises a variation tracking circuit coupled to the signal path, wherein the variation tracking circuit comprises a tracking resistor have a tracking resistance, and wherein a product of the tracking resistance and the path capacitance is substantially constant over process variation.