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    Method of generating precise and PVT-stable time delay or frequency using CMOS circuits
    1.
    发明授权
    Method of generating precise and PVT-stable time delay or frequency using CMOS circuits 有权

    公开(公告)号：US10812056B1

    公开(公告)日：2020-10-20

    申请号：US16722572

    申请日：2019-12-20

    Applicant: QUALCOMM Incorporated

    Inventor： Zhengzheng Wu ,  Xu Zhang ,  Xuhao Huang

    IPC: H03K5/134 ,  H03K3/03 ,  H03K5/00

    Abstract: A method of generating precise and PVT-stable time delay or frequency using CMOS circuits is disclosed. In some implementations, the method includes providing a reference voltage using a resistive module at a positive input terminal of an operational amplifier, coupling gates of a pair of p-type metal oxide semiconductor (pMOS) transistors and a compensation capacitor to an output terminal of the operational amplifier to generate a first bias signal, and coupling a pair of n-type metal oxide semiconductor (nMOS) transistors to a negative terminal of the operational amplifier to generate a second bias signal at the negative terminal, wherein the pair of nMOS transistors is substantially the same as a pair of nMOS transistors in the CMOS delay circuit.

    Power and area efficient digital-to-time converter with improved stability
    2.
    发明授权
    Power and area efficient digital-to-time converter with improved stability 有权

    公开(公告)号：US11177819B1

    公开(公告)日：2021-11-16

    申请号：US17111208

    申请日：2020-12-03

    Applicant: QUALCOMM Incorporated

    Inventor： Zhengzheng Wu ,  Chao Song ,  Karthik Nagarajan

    IPC: H03M1/06 ,  H03M1/82 ,  G04F10/00

    Abstract: A digital-to-time converter (DTC) converts a digital code into a time delay using a capacitor digital-to-analog converter (CDAC) that functions as a charging capacitor. The DTC includes a switched capacitor voltage-to-current converter for the formation of a charging current (or a discharging current) for charging (or for discharging) the charging capacitor responsive to a triggering clock edge that begins the time delay. A comparator compares a voltage on the charging capacitor to a threshold voltage to determine an end of the time delay.

    Method of generating precise and PVT-stable time delay or frequency using CMOS circuits
    5.
    发明授权
    Method of generating precise and PVT-stable time delay or frequency using CMOS circuits 有权

    公开(公告)号：US11196410B2

    公开(公告)日：2021-12-07

    申请号：US17022608

    申请日：2020-09-16

    Applicant: QUALCOMM Incorporated

    Inventor： Zhengzheng Wu ,  Xu Zhang ,  Xuhao Huang

    IPC: H03K5/134 ,  H03K3/03 ,  H03K5/00

    Abstract: A method of generating precise and PVT-stable time delay or frequency using CMOS circuits is disclosed. In some implementations, the method includes providing a reference voltage using a resistive module at a positive input terminal of an operational amplifier, coupling gates of a pair of p-type metal oxide semiconductor (pMOS) transistors and a compensation capacitor to an output terminal of the operational amplifier to generate a first bias signal, and coupling a pair of n-type metal oxide semiconductor (nMOS) transistors to a negative terminal of the operational amplifier to generate a second bias signal at the negative terminal, wherein the pair of nMOS transistors is substantially the same as a pair of nMOS transistors in the CMOS delay circuit.

    Adaptive gate-biased field effect transistor for low-dropout regulator
    6.
    发明授权
    Adaptive gate-biased field effect transistor for low-dropout regulator 有权

    公开(公告)号：US10545523B1

    公开(公告)日：2020-01-28

    申请号：US16170700

    申请日：2018-10-25

    Applicant: QUALCOMM Incorporated

    Inventor： Zhengzheng Wu ,  Chao Song

    IPC: G05F1/595 ,  G05F1/575

    Abstract: A load circuit of a low-dropout (LDO) regulator is disclosed herein according to certain aspects. The load circuit includes a field effect transistor having a source coupled to a supply rail, a gate, and a drain coupled to a gate of a pass transistor of the LDO regulator. The load circuit also includes an adjustable voltage source coupled between the drain and the gate of the field effect transistor, and a voltage control circuit configured to detect a change in a current load through the pass transistor, and to adjust a voltage of the adjustable voltage source based on the detected change in the current load.

    Variation tracking and compensating for small capacitor
    10.
    发明授权
    Variation tracking and compensating for small capacitor 有权

    公开(公告)号：US10312891B1

    公开(公告)日：2019-06-04

    申请号：US16142476

    申请日：2018-09-26

    Applicant: QUALCOMM Incorporated

    Inventor： Chao Song ,  Zhengzheng Wu ,  Haitao Cheng ,  Ye Lu

    IPC: H03K5/00 ,  H01L49/02 ,  H01L27/06 ,  H03K19/20

    Abstract: In certain aspects, an integrated circuit comprises a signal path having a path delay from an input to an output, wherein the signal path comprises a path capacitor having a path capacitance. The integrated circuit also comprises a variation tracking circuit coupled to the signal path, wherein the variation tracking circuit comprises a tracking resistor have a tracking resistance, and wherein a product of the tracking resistance and the path capacitance is substantially constant over process variation.

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