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公开(公告)号：US11196410B2
公开(公告)日：2021-12-07
申请号：US17022608
申请日：2020-09-16
Applicant: QUALCOMM Incorporated
Inventor： Zhengzheng Wu , Xu Zhang , Xuhao Huang
Abstract: A method of generating precise and PVT-stable time delay or frequency using CMOS circuits is disclosed. In some implementations, the method includes providing a reference voltage using a resistive module at a positive input terminal of an operational amplifier, coupling gates of a pair of p-type metal oxide semiconductor (pMOS) transistors and a compensation capacitor to an output terminal of the operational amplifier to generate a first bias signal, and coupling a pair of n-type metal oxide semiconductor (nMOS) transistors to a negative terminal of the operational amplifier to generate a second bias signal at the negative terminal, wherein the pair of nMOS transistors is substantially the same as a pair of nMOS transistors in the CMOS delay circuit.
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公开(公告)号：US12101089B2
公开(公告)日：2024-09-24
申请号：US17970519
申请日：2022-10-20
Applicant: QUALCOMM Incorporated
Inventor： Xu Zhang , Xuhao Huang
IPC: H03K19/01 , H03K3/037 , H03K19/0185 , H04M1/02
CPC classification number: H03K19/018521 , H03K3/037 , H04M1/026
Abstract: A level-shifter is provided with a first transistor and a second transistor. The first transistor functions to discharge an internal node responsive to an assertion of an inverted input signal to a first power supply voltage. A second transistor functions to discharge an inverted level-shifter output signal responsive to an assertion of an input signal to the first power supply voltage. An inverter inverts the inverted level-shifter output signal to form a level-shifter output signal that is asserted to a second power supply voltage responsive to the assertion of the input signal.
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3.发明授权公开(公告)号：US11705897B2
公开(公告)日：2023-07-18
申请号：US17495608
申请日：2021-10-06
Applicant: QUALCOMM Incorporated
Inventor： Xu Zhang , Xuhao Huang , Shitong Zhao
CPC classification number: H03K5/14 , G05F1/56 , H03F3/45475 , H03K3/0315 , H04B1/40
Abstract: An aspect relates to an apparatus, including: a ring oscillator coupled between a first node and a first voltage rail; a control circuit coupled to the first node; a delay line coupled between a second node and the first voltage rail; and a voltage regulator including an input coupled to the first node and an output coupled to the second node.
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公开(公告)号：US10812056B1
公开(公告)日：2020-10-20
申请号：US16722572
申请日：2019-12-20
Applicant: QUALCOMM Incorporated
Inventor： Zhengzheng Wu , Xu Zhang , Xuhao Huang
Abstract: A method of generating precise and PVT-stable time delay or frequency using CMOS circuits is disclosed. In some implementations, the method includes providing a reference voltage using a resistive module at a positive input terminal of an operational amplifier, coupling gates of a pair of p-type metal oxide semiconductor (pMOS) transistors and a compensation capacitor to an output terminal of the operational amplifier to generate a first bias signal, and coupling a pair of n-type metal oxide semiconductor (nMOS) transistors to a negative terminal of the operational amplifier to generate a second bias signal at the negative terminal, wherein the pair of nMOS transistors is substantially the same as a pair of nMOS transistors in the CMOS delay circuit.
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