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公开(公告)号：US20160380193A1
公开(公告)日：2016-12-29
申请号：US15262703
申请日：2016-09-12
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hsia-Wei Chen , Wen-Ting Chu , Kuo-Chi Tu , Chih-Yang Chang , Chin-Chieh Yang , Yu-Wen Liao , Wen-Chun You , Sheng-Hung Shih
CPC classification number: H01L45/1233 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/08 , H01L45/085 , H01L45/12 , H01L45/122 , H01L45/124 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/16 , H01L45/1666 , H01L45/1683
Abstract: Some embodiments relate to an integrated circuit device. The integrated circuit device includes a resistive random access memory (RRAM) cell, which includes a top electrode and a bottom electrode that are separated by a RRAM dielectric layer. The top electrode of the RRAM cell has a recess in its upper surface. A via is disposed over the RRAM cell and contacts the top electrode within the recess.
Abstract translation: 一些实施例涉及集成电路设备。 集成电路装置包括电阻随机存取存储器（RRAM）单元，其包括由RRAM介电层分离的顶电极和底电极。 RRAM单元的顶部电极在其上表面具有凹部。 通孔设置在RRAM单元上方并与凹部内的顶部电极接触。
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公开(公告)号：US20150325786A1
公开(公告)日：2015-11-12
申请号：US14803377
申请日：2015-07-20
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chih-Yang Chang , Wen-Ting Chu , Kuo-Chi Tu , Yu-Wen Liao , Hsia-Wei Chen , Chin-Chieh Yang , Sheng-Hung Shih , Wen-Chun You
IPC: H01L45/00
CPC classification number: H01L45/124 , H01L27/2436 , H01L45/04 , H01L45/06 , H01L45/065 , H01L45/08 , H01L45/085 , H01L45/10 , H01L45/12 , H01L45/1206 , H01L45/1213 , H01L45/122 , H01L45/1226 , H01L45/1233 , H01L45/1246 , H01L45/1253 , H01L45/126 , H01L45/1266 , H01L45/1273 , H01L45/1286 , H01L45/1293 , H01L45/14 , H01L45/141 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/148 , H01L45/149 , H01L45/16 , H01L45/1608 , H01L45/1616 , H01L45/1625 , H01L45/1633 , H01L45/1641 , H01L45/165 , H01L45/1658 , H01L45/1666 , H01L45/1675 , H01L45/1683 , H01L45/1691
Abstract: The present disclosure relates to a method of forming a resistive random access memory (RRAM) cell. The method forms a bottom electrode over a bottom electrode via. The method further forms a variable resistive dielectric layer over the bottom electrode, and a top electrode over the variable resistive dielectric layer. The method forms a top electrode via vertically extending outward from an upper surface of the top electrode at a position centered along a first axis that is laterally offset from a second axis centered upon the bottom electrode via. The top electrode via has a smaller width than the top electrode. Laterally offsetting the top electrode via from the bottom electrode via provides the top electrode via with good contact resistance.
Abstract translation: 本公开涉及一种形成电阻随机存取存储器（RRAM）单元的方法。 该方法在底部电极通孔上形成底部电极。 该方法进一步在底部电极上形成可变电阻介质层，以及在可变电阻介质层上形成顶部电极。 该方法通过从顶部电极的上表面向外垂直延伸的形式形成顶部电极，所述顶部电极沿着第一轴线位于以与底部电极通孔为中心的第二轴线侧向偏移的位置。 顶部电极通孔具有比顶部电极更小的宽度。 顶部电极通孔从底部电极通过提供顶部电极通孔具有良好的接触电阻。
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公开(公告)号：US09076522B2
公开(公告)日：2015-07-07
申请号：US14041916
申请日：2013-09-30
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Wen-Chun You , Kuo-Chi Tu , Chih-Yang Chang , Hsia-Wei Chen , Yu-Wen Liao , Chin-Chieh Yang , Sheng-Hung Shih , Wen-Ting Chu
CPC classification number: G11C13/003 , G11C13/0002 , G11C13/0059 , G11C13/0069 , G11C13/0097 , G11C2013/0071 , G11C2213/79
Abstract: A method is disclosed that includes the operations outlined below. A first voltage is applied to a gate of an access transistor of each of a row of memory cells during a reset operation, wherein a first source/drain of the access transistor is electrically connected to a first electrode of a resistive random access memory (RRAM) device in the same memory cell. An inhibition voltage is applied to a second electrode of the RRAM device or to a second source/drain of the access transistor of each of a plurality of unselected memory cells when the first voltage is applied to the gate of the access transistor.
Abstract translation: 公开了一种包括以下概述的操作的方法。 在复位操作期间，第一电压被施加到每行存储单元的存取晶体管的栅极，其中存取晶体管的第一源极/漏极电连接到电阻随机存取存储器（RRAM）的第一电极 ）设备在同一个存储单元中。 当第一电压被施加到存取晶体管的栅极时，抑制电压被施加到RRAM器件的第二电极或多个未选择存储器单元中的每一个的存取晶体管的第二源极/漏极。
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公开(公告)号：US20240373645A1
公开(公告)日：2024-11-07
申请号：US18777063
申请日：2024-07-18
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Tzu-Yu Chen , Kuo-Chi Tu , Fu-Chen Chang , Chih-Hsiang Chang , Sheng-Hung Shih
Abstract: In an embodiment, a structure includes one or more first transistors in a first region of a device, the one or more first transistors supporting a memory access function of the device. The structure includes one or more ferroelectric random access memory (FeRAM) capacitors in a first inter-metal dielectric (IMD) layer over the one or more first transistors in the first region. The structure also includes one or more metal-ferroelectric insulator-metal (MFM) decoupling capacitors in the first IMD layer in a second region of the device. The MFM capacitors may include two or more capacitors coupled in series to act as a voltage divider.
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公开(公告)号：US20200098983A1
公开(公告)日：2020-03-26
申请号：US16693566
申请日：2019-11-25
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hsia-Wei Chen , Wen-Ting Chu , Kuo-Chi Tu , Chih-Yang Chang , Chin-Chieh Yang , Yu-Wen Liao , Wen-Chun You , Sheng-Hung Shih
Abstract: Some embodiments relate to a device. The device includes a top electrode and a via disposed over the top electrode. A peripheral upper surface of the top electrode is above a central upper surface of the top electrode, and a tapered inner sidewall of the top electrode connects the peripheral upper surface to the central upper surface. The via establishes electrical contact with the tapered inner sidewall but is spaced apart from the central upper surface.
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Patent Agency Ranking
公开(公告)号：US10566519B2
公开(公告)日：2020-02-18
申请号：US15823012
申请日：2017-11-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hsia-Wei Chen , Chih-Yang Chang , Chin-Chieh Yang , Jen-Sheng Yang , Sheng-Hung Shih , Tung-Sheng Hsiao , Wen-Ting Chu , Yu-Wen Liao , I-Ching Chen
IPC: H01L43/02 , H01L23/538 , H01L43/12 , H01L27/22 , H01L45/00 , H01L21/768 , H01L27/24 , H01L43/08
Abstract: Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.
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公开(公告)号：US20190058109A1
公开(公告)日：2019-02-21
申请号：US15823012
申请日：2017-11-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hsia-Wei Chen , Chih-Yang Chang , Chin-Chieh Yang , Jen-Sheng Yang , Sheng-Hung Shih , Tung-Sheng Hsiao , Wen-Ting Chu , Yu-Wen Liao , I-Ching Chen
IPC: H01L43/02 , H01L43/12 , H01L23/538
Abstract: Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.
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公开(公告)号：US10164185B2
公开(公告)日：2018-12-25
申请号：US15702136
申请日：2017-09-12
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Sheng-Hung Shih , Kuo-Chi Tu , Chih-Yang Chang , Hsia-Wei Chen , Chin-Chieh Yang , Jen-Sheng Yang , Wen-Ting Chu , Yu-Wen Liao
Abstract: In some embodiments, the present disclosure relates to a method of operating an RRAM cell having a PMOS access transistor. The method may be performed by turning on a PMOS transistor having a drain terminal coupled to a lower electrode of an RRAM device. A first voltage is provided to a source terminal of the PMOS transistor, and a second voltage is provided to a bulk terminal of the PMOS transistor. The second voltage is larger than the first voltage. A third voltage is provided to an upper electrode of the RRAM device. The third voltage is larger than the first voltage.
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公开(公告)号：US09934853B2
公开(公告)日：2018-04-03
申请号：US15425213
申请日：2017-02-06
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chin-Chieh Yang , Chih-Yang Chang , Chang-Sheng Liao , Hsia-Wei Chen , Jen-Sheng Yang , Kuo-Chi Tu , Sheng-Hung Shih , Wen-Ting Chu , Manish Kumar Singh , Chi-Tsai Chen
CPC classification number: G11C13/004 , G11C11/1653 , G11C11/1655 , G11C11/1657 , G11C11/1673 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C2213/79 , G11C2213/82
Abstract: The present disclosure relates to a method and apparatus for performing a read operation of an RRAM cell, which applies a non-zero bias voltage to unselected bit-lines and select-lines to increase a read current window without damaging corresponding access transistors. In some embodiments, the method may be performed by activating a word-line coupled to a row of RRAM cells comprising a selected RRAM device by applying a first read voltage to the word-line. A second read voltage is applied to a bit-line coupled to a first electrode of the selected RRAM device. One or more non-zero bias voltages are applied to bit-lines and select-lines coupled to RRAM cells, within the row of RRAM cells, having unselected RRAM devices.
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公开(公告)号：US20170140820A1
公开(公告)日：2017-05-18
申请号：US15399977
申请日：2017-01-06
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Sheng-Hung Shih , Kuo-Chi Tu , Chih-Yang Chang , Hsia-Wei Chen , Chin-Chieh Yang , Jen-Sheng Yang , Wen-Ting Chu , Yu-Wen Liao
CPC classification number: H01L45/1273 , G11C13/003 , G11C13/0038 , G11C13/0069 , G11C13/0097 , G11C2013/0071 , G11C2013/0083 , G11C2213/79 , H01L27/2427 , H01L27/2436 , H01L27/2481 , H01L45/08 , H01L45/085 , H01L45/1233 , H01L45/1253 , H01L45/1266 , H01L45/146 , H01L45/16 , H01L45/1675
Abstract: In some embodiments, the present disclosure relates to a method of operating an RRAM cell having a PMOS access transistor. The method may be performed by forming an initial conductive filament within a dielectric data storage layer of an RRAM cell having a bottom electrode connected to a drain terminal of a PMOS transistor and a top electrode separated from the bottom electrode by the dielectric data storage layer. The initial conductive filament is formed by turning on the PMOS transistor by providing a substantially zero first forming voltage to a gate terminal of the PMOS transistor, by providing a substantially zero second forming voltage to a source terminal of the PMOS transistor, by providing a first non-zero forming voltage to a bulk terminal of the PMOS transistor, and by providing a second non-zero forming voltage to the top electrode.
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