公开(公告)号：US20170005095A1

公开(公告)日：2017-01-05

申请号：US15267328

申请日：2016-09-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Ling-Sung Wang ,  Chih-Mu Huang ,  Cing-Yao Chan ,  Chun-Ying Wang ,  Jen-Pan Wang

IPC: H01L27/092 ,  H01L29/165 ,  H01L29/10 ,  H01L21/306 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/16 ,  H01L29/06

CPC classification number: H01L27/0928 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02694 ,  H01L21/30604 ,  H01L21/823807 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66651 ,  H01L29/7842

Abstract: The present disclosure relates to a transistor device having a channel region comprising a sandwich film stack with a plurality of different layers that improve device performance, and an associated apparatus. In some embodiments, the transistor device has a source region and a drain region disposed within a semiconductor substrate. A sandwich film stack is laterally positioned between the source region and the drain region. The sandwich film stack has a lower layer, a middle layer of a carbon doped semiconductor material disposed over the lower layer, and an upper layer disposed over the middle layer. A gate structure is disposed over the sandwich film stack. The gate structure is configured to control a flow of charge carriers in a channel region located between the source region and the drain region.

Abstract translation: 本公开涉及具有沟道区的晶体管器件，该晶体管器件包括具有提高器件性能的多个不同层的夹层膜堆叠以及相关联的器件。 在一些实施例中，晶体管器件具有设置在半导体衬底内的源极区域和漏极区域。 夹层薄膜叠层横向放置在源区和漏区之间。 夹层膜堆叠具有下层，设置在下层上的碳掺杂半导体材料的中间层和设置在中间层上的上层。 栅极结构设置在夹层膜堆叠之上。 栅极结构被配置为控制位于源极区域和漏极区域之间的沟道区域中的电荷载流子的流动。

公开(公告)号：US09318371B2

公开(公告)日：2016-04-19

申请号：US14189155

申请日：2014-02-25

Applicant: Taiwan Semiconductor Manufacturing CO., LTD.

Inventor： Ru-Shang Hsiao ,  Ling-Sung Wang ,  Chih-Mu Huang ,  Chih-Fu Chang

IPC: H01L23/34 ,  H01L21/76 ,  H01L21/762 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L21/76232 ,  H01L21/76224 ,  H01L21/76297 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: A semiconductor device includes a semiconductor substrate, an active region and a trench isolation. The active region is formed in the semiconductor substrate. The trench isolation is disposed adjacent to the active region. The trench isolation includes a lower portion and an upper portion. The upper portion is located on the lower portion. The upper portion has a width gradually decreased from a junction between the upper portion and the lower portion toward a top of the trench isolation. In a method for fabricating the semiconductor device, at first, the semiconductor substrate is etched to form a trench in the semiconductor substrate. Then, an insulator fills the trench to form the trench isolation. Thereafter, the gate structure is formed on the semiconductor substrate. Then, the semiconductor substrate is etched to form a recess adjacent to the trench isolation. Thereafter, at least one doped epitaxial layer grows in the recess.

Abstract translation: 半导体器件包括半导体衬底，有源区和沟槽隔离。 在半导体衬底中形成有源区。 沟槽隔离设置在有源区附近。 沟槽隔离包括下部和上部。 上部位于下部。 上部具有从上部和下部之间的接合部朝向沟槽隔离的顶部逐渐减小的宽度。 在制造半导体器件的方法中，首先蚀刻半导体衬底以在半导体衬底中形成沟槽。 然后，绝缘体填充沟槽以形成沟槽隔离。 此后，在半导体衬底上形成栅极结构。 然后，蚀刻半导体衬底以形成与沟槽隔离相邻的凹部。 此后，至少一个掺杂的外延层在凹槽中生长。

公开(公告)号：US09318368B2

公开(公告)日：2016-04-19

申请号：US14080631

申请日：2013-11-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Fu-Cheng Chang ,  Chai-Der Yen ,  Fu-Tsun Tsai ,  Chi-Cherng Jeng ,  Chih-Mu Huang

IPC: H01L21/76 ,  H01L21/762 ,  G03F1/00

CPC classification number: H01L21/76229 ,  G03F1/00 ,  H01L21/0274 ,  H01L21/3083

Abstract: In a method for manufacturing a dual shallow trench isolation structure, a substrate is provided, and a mask layer is formed on the substrate. The mask layer is patterned by using a photomask to form at least one first hole and at least one second hole in the mask layer, in which a depth of the at least one first hole is different from a depth of the at least one second hole. The mask layer and the substrate are etched to form at least one first trench having a first depth and at least one second trench having a second depth, in which the first depth is different from the second depth. The remaining mask layer is removed. A first isolation layer and A second isolation layer are respectively formed in the at least one first trench and the at least one second trench.

Abstract translation: 在制造双浅沟槽隔离结构的方法中，提供衬底，并且在衬底上形成掩模层。 通过使用光掩模来对掩模层进行构图，以在掩模层中形成至少一个第一孔和至少一个第二孔，其中至少一个第一孔的深度不同于至少一个第二孔的深度 。 蚀刻掩模层和衬底以形成具有第一深度的至少一个第一沟槽和具有第二深度的至少一个第二沟槽，其中第一深度不同于第二深度。 剩下的掩模层被去除。 第一隔离层和第二隔离层分别形成在至少一个第一沟槽和至少一个第二沟槽中。

公开(公告)号：US20150200299A1

公开(公告)日：2015-07-16

申请号：US14224961

申请日：2014-03-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： I-Chih CHEN ,  Ying-Lang Wang ,  Chih-Mu Huang ,  Ying-Hao Chen ,  Wen-Chang Kuo ,  Jung-Chi Jeng

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L29/161 ,  H01L29/167

CPC classification number: H01L29/7848 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66628 ,  H01L29/66636

Abstract: A semiconductor device and a method of fabricating the semiconductor device are provided. The semiconductor device includes a substrate; a source/drain region having a first dopant in the substrate; a barrier layer having a second dopant formed around the source/drain region in the substrate. When a semiconductor device is scaled down, the doped profile in source/drain regions might affect the threshold voltage uniformity, the provided semiconductor device may improve the threshold voltage uniformity by the barrier layer to control the doped profile.

Abstract translation: 提供半导体器件和制造半导体器件的方法。 半导体器件包括衬底; 在衬底中具有第一掺杂剂的源/漏区; 阻挡层，其具有形成在衬底中的源极/漏极区周围的第二掺杂物。 当半导体器件按比例缩小时，源极/漏极区域中的掺杂分布可能影响阈值电压均匀性，所提供的半导体器件可以通过阻挡层来改善阈值电压均匀性以控制掺杂分布。

公开(公告)号：US10516048B2

公开(公告)日：2019-12-24

申请号：US15804887

申请日：2017-11-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

Inventor： I-Chih Chen ,  Ying-Lang Wang ,  Chih-Mu Huang ,  Ying-Hao Chen ,  Wen-Chang Kuo ,  Jung-Chi Jeng

IPC: H01L29/78 ,  H01L29/167 ,  H01L29/08 ,  H01L29/66 ,  H01L29/165

Abstract: A method of fabricating a semiconductor device includes following steps. A trench is formed in a substrate. A barrier layer and an epitaxy layer are formed in sequence in the trench. The barrier layer has a first dopant. A source/drain recess cavity is formed by etching at least the epitaxial layer. A source/drain region is formed in the source/drain recess cavity. The source/drain region has a second dopant.

公开(公告)号：US10096672B2

公开(公告)日：2018-10-09

申请号：US15651751

申请日：2017-07-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： I-Chih Chen ,  Chih-Mu Huang ,  Fu-Tsun Tsai ,  Meng-Yi Wu ,  Yung-Fa Lee ,  Ying-Lang Wang

IPC: H01L21/425 ,  H01L21/02 ,  H01L29/06 ,  H01L29/78

Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type region including a first conductivity type impurity. A first gate structure is on the semiconductor substrate overlying the first conductivity type region. A second conductivity type region including a second conductivity type impurity is formed in the semiconductor substrate. A barrier layer is located between the first conductivity type region and the second conductivity type region. The barrier layer prevents diffusion of the second conductivity type impurity from the second conductivity type region into the first conductivity type region.

公开(公告)号：US09728637B2

公开(公告)日：2017-08-08

申请号：US14080313

申请日：2013-11-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

Inventor： Jung-Chi Jeng ,  I-Chih Chen ,  Wen-Chang Kuo ,  Ying-Hao Chen ,  Ru-Shang Hsiao ,  Chih-Mu Huang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/7833 ,  H01L29/0649 ,  H01L29/6659

Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and an isolation structure in the semiconductor substrate and surrounding an active region of the semiconductor substrate. The semiconductor device also includes a gate over the semiconductor substrate, and the gate has an intermediate portion over the active region and two end portions connected to the intermediate portion, and the end portions are over the isolation structure. The semiconductor device further includes a support film over the isolation structure and covering the isolation structure and at least one of the end portions of the gate. The support film exposes the active region and the intermediate portion of the gate.

公开(公告)号：US09634122B2

公开(公告)日：2017-04-25

申请号：US14205841

申请日：2014-03-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Ling-Sung Wang ,  Chih-Mu Huang ,  Chia-Ming Chang

IPC: H01L21/46 ,  H01L29/66 ,  H01L29/06 ,  H01L21/762 ,  H01L21/28 ,  H01L29/423

CPC classification number: H01L29/66795 ,  H01L21/28114 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/785

Abstract: Some embodiments relate to an integrated circuit (IC) including one or more field-effect transistor devices. A field effect transistor device includes source/drain regions disposed in an active region of a semiconductor substrate and separated from one another along a first direction by a channel region. A shallow trench isolation (STI) region, which has an upper STI surface, laterally surrounds the active region. The STI region includes trench regions, which have lower trench surfaces below the upper STI surface and which extend from opposite sides of the channel region in a second direction which intersects the first direction. A metal gate electrode extends in the second direction and has lower portions which are disposed in the trench regions and which are separated from one another by the channel region. The metal gate electrode has an upper portion bridging over the channel region to couple the lower portions to one another.