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    SCAN FLIP-FLOP, FLIP-FLOP AND SCAN TEST CIRCUIT INCLUDING THE SAME
    21.
    发明申请
    SCAN FLIP-FLOP, FLIP-FLOP AND SCAN TEST CIRCUIT INCLUDING THE SAME 有权

    公开(公告)号：US20210152162A1

    公开(公告)日：2021-05-20

    申请号：US16993946

    申请日：2020-08-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Raheel Azmat ,  Jaehyoung Lim ,  Taehyung Kim ,  Jinwoo Jeong ,  Jaeseok Yang

    IPC: H03K3/037 ,  G01R31/3177 ,  G01R31/317

    Abstract: A scan flip-flop includes a multiplexer, a first latch, a second latch, an output buffer and a clock buffer. The multiplexer selects one of a data input signal and a scan input signal based on an operation mode. The first latch latches an output of the multiplexer. The second latch latches an output of the first latch. The output buffer generates an output signal based on an output of the second latch. The clock buffer generates a first clock signal and a second clock signal that control operation of the first latch and the second latch. The first latch, the second latch, and the clock buffer are sequentially arranged along a first direction. Each of the multiplexer and the output buffer is adjacent the first latch, the second latch, or the clock buffer along a second direction intersecting the first direction. A first clock line supplying the first clock signal and a second clock line supplying the second clock signal have a cross couple connection.

    SEMICONDUCTOR DEVICES INCLUDING FINFETS AND LOCAL INTERCONNECT LAYERS AND METHODS OF FABRICATING THE SAME
    25.
    发明申请
    SEMICONDUCTOR DEVICES INCLUDING FINFETS AND LOCAL INTERCONNECT LAYERS AND METHODS OF FABRICATING THE SAME 有权
    包括FinFET和局部互连层的半导体器件及其制造方法

    公开(公告)号：US20150194427A1

    公开(公告)日：2015-07-09

    申请号：US14534536

    申请日：2014-11-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Rwik Sengupta ,  Raheel Azmat

    IPC: H01L27/088 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L21/8234

    CPC classification number: H01L27/0886 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/0207

    Abstract: Semiconductor devices and methods of forming the same are provided. The semiconductor devices may include a finFET, a metal routing layer, a first local interconnect layer, and a second local interconnect layer. The finFET may include a channel, a first source/drain region, a second source/drain region, and a gate stack. The metal routing layer may be separated from the finFET in a vertical direction. The first local interconnect layer may include a first local interconnect that contacts a first metal route in the metal routing layer and that electrically connects to the first source/drain region. The second local interconnect layer may include a second local interconnect that contacts a second metal route in the metal routing layer and that electrically connects to the gate stack.

    Abstract translation: 提供了半导体器件及其形成方法。 半导体器件可以包括finFET，金属布线层，第一局部互连层和第二局部互连层。 finFET可以包括沟道，第一源极/漏极区域，第二源极/漏极区域和栅极堆叠。 金属布线层可以在垂直方向上与finFET分离。 第一局部互连层可以包括接触金属布线层中的第一金属路径并且电连接到第一源极/漏极区的第一局部互连。 第二局部互连层可以包括接触金属布线层中的第二金属路径并且电连接到栅极堆叠的第二局部互连。

    Semiconductor integrated circuit
    26.
    发明授权
    Semiconductor integrated circuit 有权

    公开(公告)号：US11631672B2

    公开(公告)日：2023-04-18

    申请号：US16997335

    申请日：2020-08-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jinwoo Jeong ,  Raheel Azmat

    IPC: H01L27/092 ,  H01L27/02

    Abstract: A semiconductor integrated circuit includes a substrate, and a standard cell on the substrate. The standard cell includes a first wiring structure electrically connecting a first gate pattern to a fourth gate pattern, and a second wiring structure electrically connecting a second gate pattern to a third gate pattern. The first wiring structure includes a first lower wiring layer, a second lower wiring layer, first and second intermediate wiring layers, and a first upper wiring layer. The second wiring structure includes a third lower wiring layer, a fourth lower wiring layer, third and fourth intermediate wiring layers, and a second upper wiring layer.

    Semiconductor device
    28.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11348918B2

    公开(公告)日：2022-05-31

    申请号：US16864260

    申请日：2020-05-01

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Taehyung Kim ,  Jinwoo Jeong ,  Jiwook Kwon ,  Raheel Azmat ,  Kwanyoung Chun

    IPC: H01L27/092 ,  H01L23/528 ,  H01L27/11 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/02

    Abstract: A semiconductor device including a substrate; first to third active patterns on an upper portion of the substrate, the active patterns being sequentially arranged in a first direction and extending in a second direction crossing the first direction; first to third power rails respectively connected to the first to third active patterns, wherein a width of the second active pattern in the first direction is at least two times a width of the first active pattern in the first direction and is at least two times a width of the third active pattern in the first direction, the first active pattern is not vertically overlapped with the first power rail, the second active pattern is vertically overlapped with the second power rail, and the third active pattern is not vertically overlapped with the third power rail.

    Scan flip-flop, flip-flop and scan test circuit including the same
    29.
    发明授权
    Scan flip-flop, flip-flop and scan test circuit including the same 有权

    公开(公告)号：US11223344B2

    公开(公告)日：2022-01-11

    申请号：US16993946

    申请日：2020-08-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Raheel Azmat ,  Jaehyoung Lim ,  Taehyung Kim ,  Jinwoo Jeong ,  Jaeseok Yang

    IPC: H03K3/037 ,  G01R31/317 ,  G01R31/3177

    Abstract: A scan flip-flop includes a multiplexer, a first latch, a second latch, an output buffer and a clock buffer. The multiplexer selects one of a data input signal and a scan input signal based on an operation mode. The first latch latches an output of the multiplexer. The second latch latches an output of the first latch. The output buffer generates an output signal based on an output of the second latch. The clock buffer generates a first clock signal and a second clock signal that control operation of the first latch and the second latch. The first latch, the second latch, and the clock buffer are sequentially arranged along a first direction. A first clock line supplying the first clock signal and a second clock line supplying the second clock signal have a cross couple connection.

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