公开(公告)号：US10177093B2

公开(公告)日：2019-01-08

申请号：US15497283

申请日：2017-04-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyo-Jin Kim ,  Chang-Hwa Kim ,  Hwi-Chan Jun ,  Chul-Hong Park ,  Jae-Seok Yang ,  Kwan-Young Chun

IPC: H01L23/535 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the device including gate structures on a substrate; source/drain layers on portions of the substrate that are adjacent the gate structures, respectively; first contact plugs contacting upper surfaces of the source/drain layers, respectively; a second contact plug contacting one of the gate structures, a sidewall of the second contact plug being covered by an insulating spacer; and a third contact plug commonly contacting an upper surface of at least one of the gate structures and at least one of the first contact plugs, at least a portion of a sidewall of the third contact plug not being covered by an insulating spacer.

公开(公告)号：US10957765B2

公开(公告)日：2021-03-23

申请号：US16051667

申请日：2018-08-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Pan-Jae Park ,  Jae-Seok Yang ,  Young-Hun Kim ,  Hae-Wang Lee ,  Kwan-Young Chun

IPC: H01L29/08 ,  H01L27/088 ,  H01L27/02 ,  H01L27/118 ,  H01L27/092 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

Abstract: A semiconductor device is provided including a substrate, a first gate structure, a first contact plug and a power rail. The substrate includes first and second cell regions extending in a first direction, and a power rail region connected to each of opposite ends of the first and second cell regions in a second direction. The first gate structure extends in the second direction from a boundary area between the first and second cell regions to the power rail region. The first contact plug is formed on the power rail region, and contacts an upper surface of the first gate structure. The power rail extends in the first direction on the power rail region, and is electrically connected to the first contact plug. The power rail supplies a turn-off signal to the first gate structure through the first contact plug to electrically insulate the first and second cell regions.

公开(公告)号：US10886227B2

公开(公告)日：2021-01-05

申请号：US16217220

申请日：2018-12-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyo-Jin Kim ,  Chang-Hwa Kim ,  Hwi-Chan Jun ,  Chui-Hong Park ,  Jae-Seok Yang ,  Kwan-Young Chun

IPC: H01L23/535 ,  H01L27/088 ,  H01L21/84 ,  H01L27/12 ,  H01L21/768 ,  H01L29/08 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the device including gate structures on a substrate; source/drain layers on portions of the substrate that are adjacent the gate structures, respectively; first contact plugs contacting upper surfaces of the source/drain layers, respectively; a second contact plug contacting one of the gate structures, a sidewall of the second contact plug being covered by an insulating spacer; and a third contact plug commonly contacting an upper surface of at least one of the gate structures and at least one of the first contact plugs, at least a portion of a sidewall of the third contact plug not being covered by an insulating spacer.

公开(公告)号：US11461521B2

公开(公告)日：2022-10-04

申请号：US16401820

申请日：2019-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Raheel Azmat ,  Sidharth Rastogi ,  Chul-Hong Park ,  Jae-Seok Yang ,  Kwan-Young Chun

IPC: G06F30/327 ,  H01L27/02 ,  G06F30/398

Abstract: An integrated circuit including a standard cell includes: a plurality of first wells extending in a first horizontal direction with a first width and of a first conductivity type; and a plurality of second wells extending in the first horizontal direction with a second width and having a second conductivity type, wherein the plurality of first wells and the plurality of second wells are alternately arranged in a second horizontal direction that is orthogonal to the first horizontal direction, and when m and n are integers greater than or equal to 3, the standard cell has a length in the second horizontal direction, the length being equal to a sum of m times a half of the first width and n times a half of the second width.

公开(公告)号：US11935835B2

公开(公告)日：2024-03-19

申请号：US17120616

申请日：2020-12-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyo-Jin Kim ,  Chang-Hwa Kim ,  Hwi-Chan Jun ,  Chul-Hong Park ,  Jae-Seok Yang ,  Kwan-Young Chun

IPC: H01L23/535 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/088 ,  H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L23/535 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/845 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/785 ,  H01L21/76831 ,  H01L21/76889 ,  H01L21/823481

Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the device including gate structures on a substrate; source/drain layers on portions of the substrate that are adjacent the gate structures, respectively; first contact plugs contacting upper surfaces of the source/drain layers, respectively; a second contact plug contacting one of the gate structures, a sidewall of the second contact plug being covered by an insulating spacer; and a third contact plug commonly contacting an upper surface of at least one of the gate structures and at least one of the first contact plugs, at least a portion of a sidewall of the third contact plug not being covered by an insulating spacer.

公开(公告)号：US09735157B1

公开(公告)日：2017-08-15

申请号：US15073908

申请日：2016-03-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwan-Young Chun ,  Yoon-Moon Park ,  Kang-Ill Seo ,  Wouns Yang

IPC: H01L27/088 ,  H01L23/528 ,  H01L27/02

CPC classification number: H01L27/0886 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/088

Abstract: A semiconductor device includes a first active area, a second active area and a first gate line. The second active area is spaced apart from the first active area. The first gate line includes a first gate part crossing the first active area along a first imaginary line, a second gate part crossing the second active area along a second imaginary line, and a third gate part connecting the first gate part and the second gate part and extending along a third imaginary line crossing the first imaginary line and the second imaginary line. The first gate part, the second gate part and the third gate part are arranged so that the first gate line has a shape of 180° rotational symmetry. A point of the rotational symmetry is located on the first gate part.