公开(公告)号：US10204902B2

公开(公告)日：2019-02-12

申请号：US15295115

申请日：2016-10-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hae-Wang Lee

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/78 ,  H01L29/10 ,  H01L23/535 ,  H01L29/08 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/51

Abstract: A semiconductor device includes a first active structure on a substrate including a first epitaxial pattern, a second epitaxial pattern and a first channel pattern between the first epitaxial pattern and the second epitaxial pattern, the first channel pattern including at least one channel pattern stacked on the substrate. A first gate structure is disposed on top and bottom surfaces of the first channel pattern. A second active structure on the substrate and includes the second epitaxial pattern, a third epitaxial pattern and a second channel pattern between the second epitaxial pattern and the third epitaxial pattern in the first direction. The second channel pattern includes at least one channel pattern stacked on the substrate. The number of stacked second channel patterns is greater than the number of stacked first channel patterns. A second gate structure is disposed on top and bottom surfaces of the second channel pattern.

公开(公告)号：US10121735B2

公开(公告)日：2018-11-06

申请号：US15794131

申请日：2017-10-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seon-Ah Nam ,  Ikuo Nakamatsu ,  Dong-Hyun Kim ,  Chul-Hong Park ,  Yun-Se Oh ,  Hae-Wang Lee ,  Ho-Jun Choi

IPC: H01L27/088 ,  H01L23/498 ,  H01L23/48 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor device includes active fins on a substrate. Gate lines each extend in the second direction on the active fins. A contact plug is positioned on the active fins. A first via is in one of the first contact plugs. A first conductive line overlaps a first via. A first distance from a first active fin on which a first gate line of the gate lines is formed to an end of the first gate line is more than a predetermined distance. A second distance from a second active fin on which the first gate line is formed to the first active fin of the active fins is equal to or less than the predetermined distance. The second active fin is spaced apart from the first contact plugs to not overlap the first contact plugs.

公开(公告)号：US12068326B2

公开(公告)日：2024-08-20

申请号：US18176463

申请日：2023-02-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Hun Kim ,  Jae-Seok Yang ,  Hae-Wang Lee

IPC: H01L27/118 ,  H01L21/8238 ,  H01L27/02

CPC classification number: H01L27/11807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/0207 ,  H01L2027/11829 ,  H01L2027/11861 ,  H01L2027/11864 ,  H01L2027/11881

Abstract: A semiconductor device includes a substrate having cell areas and power areas that are alternately arranged in a second direction. Gate structures extend in the second direction. The gate structures are spaced apart from each other in a first direction perpendicular to the second direction. Junction layers are arranged at both sides of each gate structure. The junction layers are arranged in the second direction such that each of the junction layer has a flat portion that is proximate to the power area. Cutting patterns are arranged in the power areas. The cutting patterns extend in the first direction such that each of the gate structures and each of the junction layers in neighboring cell areas are separated from each other by the cutting pattern.

公开(公告)号：US11600639B2

公开(公告)日：2023-03-07

申请号：US17087321

申请日：2020-11-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Hun Kim ,  Jae-Seok Yang ,  Hae-Wang Lee

IPC: H01L27/118 ,  H01L21/8238 ,  H01L27/02

Abstract: A semiconductor device includes a substrate having cell areas and power areas that are alternately arranged in a second direction. Gate structures extend in the second direction. The gate structures are spaced apart from each other in a first direction perpendicular to the second direction. Junction layers are arranged at both sides of each gate structure. The junction layers are arranged in the second direction such that each of the junction layer has a flat portion that is proximate to the power area. Cutting patterns are arranged in the power areas. The cutting patterns extend in the first direction such that each of the gate structures and each of the junction layers in neighboring cell areas are separated from each other by the cutting pattern.

公开(公告)号：US11710736B2

公开(公告)日：2023-07-25

申请号：US17113787

申请日：2020-12-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hae-Wang Lee

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/78 ,  H01L29/10 ,  H01L23/535 ,  H01L29/08 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/51 ,  H01L29/786

CPC classification number: H01L27/088 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823437 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/66772 ,  H01L29/785 ,  H01L29/7831 ,  H01L29/78654 ,  H01L29/78696

Abstract: A semiconductor device includes a first active structure on a substrate including a first epitaxial pattern, a second epitaxial pattern and a first channel pattern between the first epitaxial pattern and the second epitaxial pattern, the first channel pattern including at least one channel pattern stacked on the substrate. A first gate structure is disposed on top and bottom surfaces of the first channel pattern. A second active structure on the substrate and includes the second epitaxial pattern, a third epitaxial pattern and a second channel pattern between the second epitaxial pattern and the third epitaxial pattern in the first direction. The second channel pattern includes at least one channel pattern stacked on the substrate. The number of stacked second channel patterns is greater than the number of stacked first channel patterns. A second gate structure is disposed on top and bottom surfaces of the second channel pattern.

公开(公告)号：US10957765B2

公开(公告)日：2021-03-23

申请号：US16051667

申请日：2018-08-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Pan-Jae Park ,  Jae-Seok Yang ,  Young-Hun Kim ,  Hae-Wang Lee ,  Kwan-Young Chun

IPC: H01L29/08 ,  H01L27/088 ,  H01L27/02 ,  H01L27/118 ,  H01L27/092 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

Abstract: A semiconductor device is provided including a substrate, a first gate structure, a first contact plug and a power rail. The substrate includes first and second cell regions extending in a first direction, and a power rail region connected to each of opposite ends of the first and second cell regions in a second direction. The first gate structure extends in the second direction from a boundary area between the first and second cell regions to the power rail region. The first contact plug is formed on the power rail region, and contacts an upper surface of the first gate structure. The power rail extends in the first direction on the power rail region, and is electrically connected to the first contact plug. The power rail supplies a turn-off signal to the first gate structure through the first contact plug to electrically insulate the first and second cell regions.

公开(公告)号：US09425148B2

公开(公告)日：2016-08-23

申请号：US13718138

申请日：2012-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-Jun Kim ,  Hae-Wang Lee ,  Chul-Hong Park ,  Dong-Kyun Sohn ,  Jong-Shik Yoon

IPC: H01L23/538 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5384 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/76897 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53266 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices, and a method for fabricating the same, include an interlayer dielectric film pattern over a substrate, a first wiring within the interlayer dielectric film pattern and having a first length in a first direction, a second wiring within the interlayer dielectric film pattern and separated from the first wiring, and a spacer contacting the first wiring and the second wiring. The spacer electrically separates the first wiring and the second wiring from each other. The second wiring has a second length different from the first length in the first direction.

Abstract translation: 半导体器件及其制造方法包括在衬底上的层间电介质膜图案，层间电介质膜图案内的第一布线，并且具有第一方向的第一长度，层间电介质膜图案内的第二布线和 与第一布线分离，以及与第一布线和第二布线接触的间隔件。 间隔件将第一布线和第二布线彼此电分离。 第二布线具有与第一方向上的第一长度不同的第二长度。