公开(公告)号：US08952452B2

公开(公告)日：2015-02-10

申请号：US13692012

申请日：2012-12-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hong-Seong Kang ,  Yoon-Hae Kim ,  Jong-Shik Yoon

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/78 ,  H01L29/40 ,  H01L21/768 ,  H01L29/49 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/417 ,  H01L27/088

CPC classification number: H01L29/78 ,  H01L21/7682 ,  H01L21/76897 ,  H01L21/823456 ,  H01L21/823468 ,  H01L27/088 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656

Abstract: Semiconductor devices, and a method of manufacturing the same, include a gate insulating film pattern over a semiconductor substrate. A gate electrode is formed over the gate insulating film pattern. A spacer structure is formed on at least one side of the gate electrode and the gate insulating film pattern. The spacer structure includes a first insulating film spacer contacting the gate insulating film pattern, and a second insulating film spacer on an outer side of the first insulating film spacer. The semiconductor device has an air gap between the first insulating film spacer and the second insulating film spacer.

Abstract translation: 半导体器件及其制造方法包括在半导体衬底上的栅极绝缘膜图案。 在栅极绝缘膜图案上形成栅电极。 在栅电极和栅绝缘膜图案的至少一侧上形成间隔结构。 间隔结构包括与栅极绝缘膜图案接触的第一绝缘膜间隔件和在第一绝缘膜间隔件的外侧上的第二绝缘膜间隔件。 半导体器件在第一绝缘膜间隔件和第二绝缘膜间隔件之间具有气隙。

公开(公告)号：US09412693B2

公开(公告)日：2016-08-09

申请号：US14174705

申请日：2014-02-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoon-Hae Kim ,  Jong-Shik Yoon ,  Hwa-Sung Rhee

IPC: H01L27/11 ,  H01L23/525 ,  H01L49/02 ,  H01L23/485 ,  H01L23/522 ,  H01L27/06 ,  H01L21/8234 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5256 ,  H01L21/76808 ,  H01L21/76895 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5221 ,  H01L23/5223 ,  H01L23/5228 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L27/0629 ,  H01L28/20 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate having a transistor area, a gate structure disposed on the transistor area of the substrate, a first interlayer insulating layer covering the gate structure, a blocking pattern disposed on the first interlayer insulating layer, and a jumper pattern disposed on the blocking pattern. The jumper pattern includes jumper contact plugs vertically penetrating the first interlayer insulating layer to be in contact with the substrate exposed at both sides of the gate structure, and a jumper section configured to electrically connect the jumper contact plugs.

Abstract translation: 半导体器件包括具有晶体管区域的衬底，设置在衬底的晶体管区域上的栅极结构，覆盖栅极结构的第一层间绝缘层，设置在第一层间绝缘层上的阻挡图案，以及布置在 阻塞模式。 跳线图案包括垂直穿过第一层间绝缘层以与暴露在栅极结构两侧的基板接触的跨接触插塞，以及被配置为电连接跨接触头塞的跳线部分。

公开(公告)号：US20140332871A1

公开(公告)日：2014-11-13

申请号：US14174705

申请日：2014-02-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoon-Hae Kim ,  Jong-Shik Yoon ,  Hwa-Sung Rhee

IPC: H01L23/525 ,  H01L49/02

CPC classification number: H01L23/5256 ,  H01L21/76808 ,  H01L21/76895 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5221 ,  H01L23/5223 ,  H01L23/5228 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L27/0629 ,  H01L28/20 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate having a transistor area, a gate structure disposed on the transistor area of the substrate, a first interlayer insulating layer covering the gate structure, a blocking pattern disposed on the first interlayer insulating layer, and a jumper pattern disposed on the blocking pattern. The jumper pattern includes jumper contact plugs vertically penetrating the first interlayer insulating layer to be in contact with the substrate exposed at both sides of the gate structure, and a jumper section configured to electrically connect the jumper contact plugs.

Abstract translation: 半导体器件包括具有晶体管区域的衬底，设置在衬底的晶体管区域上的栅极结构，覆盖栅极结构的第一层间绝缘层，设置在第一层间绝缘层上的阻挡图案，以及布置在 阻塞模式。 跳线图案包括垂直穿过第一层间绝缘层以与暴露在栅极结构两侧的基板接触的跨接触插塞，以及被配置为电连接跨接触头塞的跳线部分。

公开(公告)号：US09425148B2

公开(公告)日：2016-08-23

申请号：US13718138

申请日：2012-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-Jun Kim ,  Hae-Wang Lee ,  Chul-Hong Park ,  Dong-Kyun Sohn ,  Jong-Shik Yoon

IPC: H01L23/538 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5384 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/76897 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53266 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices, and a method for fabricating the same, include an interlayer dielectric film pattern over a substrate, a first wiring within the interlayer dielectric film pattern and having a first length in a first direction, a second wiring within the interlayer dielectric film pattern and separated from the first wiring, and a spacer contacting the first wiring and the second wiring. The spacer electrically separates the first wiring and the second wiring from each other. The second wiring has a second length different from the first length in the first direction.

Abstract translation: 半导体器件及其制造方法包括在衬底上的层间电介质膜图案，层间电介质膜图案内的第一布线，并且具有第一方向的第一长度，层间电介质膜图案内的第二布线和 与第一布线分离，以及与第一布线和第二布线接触的间隔件。 间隔件将第一布线和第二布线彼此电分离。 第二布线具有与第一方向上的第一长度不同的第二长度。

公开(公告)号：US09209177B2

公开(公告)日：2015-12-08

申请号：US13783513

申请日：2013-03-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoon-Hae Kim ,  Jong-Shik Yoon ,  Young-Gun Ko

IPC: H01L27/12 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/823431

Abstract: Semiconductor devices are provided. The semiconductor devices may include an active pattern and a insulation layer. The semiconductor devices may include a gate that is on the active pattern and that includes a first material, and a dummy gate that is on the insulation layer and that includes a second material different from the first material.

Abstract translation: 提供半导体器件。 半导体器件可以包括有源图案和绝缘层。 半导体器件可以包括位于有源图案上的并且包括第一材料的栅极和位于绝缘层上并且包括不同于第一材料的第二材料的伪栅极。