公开(公告)号：US11848382B2

公开(公告)日：2023-12-19

申请号：US17734686

申请日：2022-05-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinwoo Jeong ,  Jaehyoung Lim

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06

CPC classification number: H01L29/785 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/66795

Abstract: A semiconductor device includes a substrate that includes a first active region and a second active region, a device isolation layer between the first active region and the second active region, a gate structure that extends in a first direction and runs across the first active region and the second active region, a first active contact pattern on the first active region on one side of the gate structure, a second active contact pattern on the second active region on another side of the gate structure, and a connection pattern that is on the device isolation layer and connects the first active contact pattern and the second active contact pattern to each other. The connection pattern extends in a second direction and runs across the gate structure. Portions of the first active contact pattern and the second active contact pattern extend in the first direction and overlap the device isolation layer.

公开(公告)号：US20210152162A1

公开(公告)日：2021-05-20

申请号：US16993946

申请日：2020-08-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Raheel Azmat ,  Jaehyoung Lim ,  Taehyung Kim ,  Jinwoo Jeong ,  Jaeseok Yang

IPC: H03K3/037 ,  G01R31/3177 ,  G01R31/317

Abstract: A scan flip-flop includes a multiplexer, a first latch, a second latch, an output buffer and a clock buffer. The multiplexer selects one of a data input signal and a scan input signal based on an operation mode. The first latch latches an output of the multiplexer. The second latch latches an output of the first latch. The output buffer generates an output signal based on an output of the second latch. The clock buffer generates a first clock signal and a second clock signal that control operation of the first latch and the second latch. The first latch, the second latch, and the clock buffer are sequentially arranged along a first direction. Each of the multiplexer and the output buffer is adjacent the first latch, the second latch, or the clock buffer along a second direction intersecting the first direction. A first clock line supplying the first clock signal and a second clock line supplying the second clock signal have a cross couple connection.

公开(公告)号：US20240128354A1

公开(公告)日：2024-04-18

申请号：US18231549

申请日：2023-08-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jisoo Park ,  Byungju Kang ,  Junghan Lee ,  Jaehyoung Lim

IPC: H01L29/66 ,  H01L23/48

CPC classification number: H01L29/66545 ,  H01L23/481 ,  H01L29/66795

Abstract: In a method of manufacturing a semiconductor device, an alignment key is formed through a portion of a substrate including first and second surfaces opposite to each other, which is adjacent to the second surface of the substrate. A transistor including a gate structure and a source/drain layer is formed on the second surface of the substrate. A portion of the substrate adjacent to the first surface of the substrate is removed to expose the alignment key. A contact plug is formed through a portion of the substrate adjacent to the first surface of the substrate to be electrically connected to the source/drain layer. A power rail is formed on the first surface of the substrate to be electrically connected to the contact plug.

公开(公告)号：US11322616B2

公开(公告)日：2022-05-03

申请号：US16781991

申请日：2020-02-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinwoo Jeong ,  Jaehyoung Lim

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06 ,  H01L29/66

Abstract: A semiconductor device includes a substrate that includes a first active region and a second active region, a device isolation layer between the first active region and the second active region, a gate structure that extends in a first direction and runs across the first active region and the second active region, a first active contact pattern on the first active region on one side of the gate structure, a second active contact pattern on the second active region on another side of the gate structure, and a connection pattern that is on the device isolation layer and connects the first active contact pattern and the second active contact pattern to each other. The connection pattern extends in a second direction and runs across the gate structure. Portions of the first active contact pattern and the second active contact pattern extend in the first direction and overlap the device isolation layer.

公开(公告)号：US11223344B2

公开(公告)日：2022-01-11

申请号：US16993946

申请日：2020-08-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Raheel Azmat ,  Jaehyoung Lim ,  Taehyung Kim ,  Jinwoo Jeong ,  Jaeseok Yang

IPC: H03K3/037 ,  G01R31/317 ,  G01R31/3177

Abstract: A scan flip-flop includes a multiplexer, a first latch, a second latch, an output buffer and a clock buffer. The multiplexer selects one of a data input signal and a scan input signal based on an operation mode. The first latch latches an output of the multiplexer. The second latch latches an output of the first latch. The output buffer generates an output signal based on an output of the second latch. The clock buffer generates a first clock signal and a second clock signal that control operation of the first latch and the second latch. The first latch, the second latch, and the clock buffer are sequentially arranged along a first direction. A first clock line supplying the first clock signal and a second clock line supplying the second clock signal have a cross couple connection.