公开(公告)号：US20240128354A1

公开(公告)日：2024-04-18

申请号：US18231549

申请日：2023-08-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jisoo Park ,  Byungju Kang ,  Junghan Lee ,  Jaehyoung Lim

IPC: H01L29/66 ,  H01L23/48

CPC classification number: H01L29/66545 ,  H01L23/481 ,  H01L29/66795

Abstract: In a method of manufacturing a semiconductor device, an alignment key is formed through a portion of a substrate including first and second surfaces opposite to each other, which is adjacent to the second surface of the substrate. A transistor including a gate structure and a source/drain layer is formed on the second surface of the substrate. A portion of the substrate adjacent to the first surface of the substrate is removed to expose the alignment key. A contact plug is formed through a portion of the substrate adjacent to the first surface of the substrate to be electrically connected to the source/drain layer. A power rail is formed on the first surface of the substrate to be electrically connected to the contact plug.

公开(公告)号：US20250157942A1

公开(公告)日：2025-05-15

申请号：US18647135

申请日：2024-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jisoo Park ,  Jung Han Lee

IPC: H01L23/544 ,  H01L29/08 ,  H01L29/66 ,  H01L29/775

Abstract: A semiconductor device includes a substrate including a logic cell region including active patterns spaced apart in a first direction and extending in a second direction different from the first direction, and an overlay key region including a back-side key pattern and a front-side key pattern, source/drain patterns on the active patterns of the logic cell region and spaced apart in the second direction, a channel pattern between the source/drain patterns, and a gate pattern extending in the first direction, crossing between the source/drain patterns, and surrounding at least a part of the channel pattern, wherein the substrate has an upper surface and a lower surface facing each other in a third direction different from the first direction and the second direction, and the back-side key pattern of the overlay key region extends into the lower surface of the substrate.

公开(公告)号：US20250142956A1

公开(公告)日：2025-05-01

申请号：US18659726

申请日：2024-05-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jisoo Park ,  JUNG HAN LEE ,  KWANYOUNG CHUN ,  Kwangmuk LEE

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L23/528 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Disclosed is a three-dimensional semiconductor device comprising a substrate including first and second regions, a first active section on the first region and including a first lower channel pattern and a first lower source/drain pattern, a second active section on the first active section and including a first upper channel pattern and a first upper source/drain pattern, a third active section on the second region and including a second lower channel pattern and a second lower source/drain pattern, a fourth active section on the third active section and including a second upper channel pattern and a second upper source/drain pattern, and a gate electrode on the first and second lower channel patterns and the first and second upper channel patterns. A first width in a first direction of the first lower channel pattern is greater than a second width in the first direction of the second lower channel pattern.