公开(公告)号：US20180212029A1

公开(公告)日：2018-07-26

申请号：US15874005

申请日：2018-01-18

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Mustafa Badaroglu ,  John Jianhong Zhu

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/66 ,  H01L29/10 ,  H01L29/06 ,  H01L29/16 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

Abstract: Semiconductor devices employing reduced area conformal contacts for reducing parasitic capacitance and improving performance, and related methods are disclosed. The area of the source/drain contacts for providing an electrical contract to a source/drain is reduced in size to reduce parasitic capacitance between a gate and the source/drain contacts for improved performance. To mitigate or avoid increase in contact resistance between the source/drain contacts and source/drain, a conformal contact layer of a desired thickness is disposed adjacent to the source/drain to reduce the source/drain contact resistance. Thus, the source/drain contacts may only have to extend down adjacent to an upper region of the source/drain to still achieve a desired, lower contact resistance with the source/drain contacts, which results in a reduced area source/drain contact for reducing parasitic capacitance.

公开(公告)号：US20180204794A1

公开(公告)日：2018-07-19

申请号：US15825231

申请日：2017-11-29

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu

IPC: H01L23/528 ,  H01L23/532 ,  H01L23/50 ,  H01L21/768 ,  H01L31/09

CPC classification number: H01L23/528 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/50 ,  H01L23/53209 ,  H01L31/09

Abstract: Aspects for reducing tip-to-tip distance between end portions of metal lines formed in an interconnect layer of an integrated circuit (IC) are provided. In one aspect, a method includes exposing a photoresist layer disposed over a hardmask layer to a light to form a metal line pattern on the photoresist layer. The metal line pattern includes metal line templates corresponding to tracks substantially parallel to an axis. The sections of the photoresist layer corresponding to the metal line pattern are removed to expose the hardmask layer according to the metal line pattern. The exposed portions of the hardmask layer are etched such that trenches are formed corresponding to the metal line pattern. The hardmask layer is directionally etched such that at least one trench is extended in a first direction along the axis. This allows the trenches to be spaced with a reduced pitch and reduced tip-to-tip distance.

公开(公告)号：US09985014B2

公开(公告)日：2018-05-29

申请号：US15266523

申请日：2016-09-15

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Mustafa Badaroglu ,  Da Yang

IPC: G06F17/50 ,  H01L27/00 ,  H01L27/02 ,  H01L29/423

CPC classification number: H01L27/0207 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5077 ,  H01L27/11807 ,  H01L29/4232 ,  H01L2027/11811

Abstract: Minimum track standard cell circuits for reduced area are provided. In one aspect, a minimum track standard cell circuit employs a first high aspect ratio voltage rail disposed over a first one-half track and configured to provide a first voltage (e.g., VDD) to the minimum track standard cell circuit. A second high aspect ratio voltage rail is disposed over a second one-half track substantially parallel to the first high aspect ratio voltage rail. The second high aspect ratio voltage rail is configured to provide a second voltage less than the first voltage (e.g., VSS) to the minimum track standard cell circuit. The minimum track standard cell circuit employs multiple tracks disposed between the first and second one-half tracks. The number of tracks can be limited based on particular factors. Minimizing tracks reduces area compared to conventional standard cell circuits.

公开(公告)号：US09941156B2

公开(公告)日：2018-04-10

申请号：US14676728

申请日：2015-04-01

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Vidhya Ramachandran ,  Christine Sung-An Hau-Riege ,  John Jianhong Zhu ,  Jeffrey Junhao Xu ,  Jihong Choi ,  Jun Chen ,  Choh Fei Yeap

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/7682 ,  H01L21/76802 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295

Abstract: Devices and methods to reduce parasitic capacitance are disclosed. A device may include a dielectric layer. The device may include first and second conductive structures and an etch stop layer proximate to the dielectric layer. The etch stop layer may define first and second openings proximate to a region of the dielectric layer between the first and second conductive structures. The device may include first and second airgaps within the region. The device may include a layer of material proximate to (e.g., on, above, or over) the etch stop layer. The layer of material proximate to the etch stop layer may cover the first and second airgaps.

公开(公告)号：US20170236841A1

公开(公告)日：2017-08-17

申请号：US15160192

申请日：2016-05-20

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Choh Fei Yeap ,  Jeffrey Junhao Xu ,  Kern Rim ,  Vladimir Machkaoutsan

IPC: H01L27/12 ,  H01L21/84 ,  H01L29/267 ,  H01L29/165 ,  H01L29/06 ,  H01L29/04

CPC classification number: H01L27/1211 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/267 ,  H01L29/66795 ,  H01L29/785

Abstract: A device includes a substrate, a fin, and an isolation layer. The device also includes an epitaxial cladding layer on a sidewall of the fin. The epitaxial cladding layer has a substantially uniform thickness and has a continuous lattice structure at an interface with the sidewall. The epitaxial cladding layer is positioned above the isolation layer.

公开(公告)号：US20170110541A1

公开(公告)日：2017-04-20

申请号：US15198892

申请日：2016-06-30

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Stanley Seungchul Song ,  Da Yang ,  Vladimir Machkaoutsan ,  Mustafa Badaroglu ,  Choh Fei Yeap

IPC: H01L29/06 ,  H01L29/16 ,  H01L21/02 ,  H01L21/306 ,  H01L21/265 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L29/0673 ,  H01L21/02603 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/125 ,  H01L29/16 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7853

Abstract: Aspects disclosed in the detailed description include nanowire channel structures of continuously stacked heterogeneous nanowires for complementary metal oxide semiconductor (CMOS) devices. Each of the nanowires has a top end portion and a bottom end portion that are narrower than a central portion. Furthermore, vertically adjacent nanowires are interconnected at the narrower top end portions and bottom end portions. This allows for connectivity between stacked nanowires and for having separation areas between vertically adjacent heterogeneous nanowires. Having the separation areas allows for gate material to be disposed over a large area of the heterogeneous nanowires and, therefore, provides strong gate control, a shorter nanowire channel structure, low parallel plate parasitic capacitance, and low parasitic channel capacitance. Having the nanowires be heterogeneous, i.e., fabricated using materials of different etching sensitivity, facilitates forming the particular cross section of the nanowires, thus eliminating the use of sacrificial masks/layers to form the heterogeneous nanowires.

公开(公告)号：US09543248B2

公开(公告)日：2017-01-10

申请号：US14819159

申请日：2015-08-05

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Junjing Bao ,  John Jianhong Zhu ,  Stanley Seungchul Song ,  Niladri Narayan Mojumder ,  Choh Fei Yeap

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768 ,  B29C67/00 ,  G05B19/418 ,  B33Y50/02

CPC classification number: H01L23/53223 ,  B29C64/386 ,  B33Y50/02 ,  G05B19/418 ,  G05B2219/45031 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76858 ,  H01L21/76871 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76882 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53219 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit device includes a first metal layer including aluminum. The integrated circuit device includes a second metal layer including an interconnect structure. The interconnect structure includes a layer of first material including aluminum. The integrated circuit device includes an inter-diffusion layer that includes aluminum. The inter-diffusion layer is proximate to the first metal layer and proximate to the layer of first material including aluminum. The integrated circuit device includes a self-forming barrier layer that includes aluminum. The self-forming barrier layer is proximate to a dielectric layer and proximate to the layer of first material including aluminum.

Abstract translation: 集成电路器件包括包括铝的第一金属层。 集成电路器件包括具有互连结构的第二金属层。 互连结构包括一层包括铝的第一材料。 集成电路器件包括包括铝的互扩散层。 互扩散层靠近第一金属层并且靠近包括铝的第一材料层。 集成电路器件包括包含铝的自形成阻挡层。 自形成阻挡层靠近电介质层并且靠近包括铝的第一材料层。

公开(公告)号：US09502414B2

公开(公告)日：2016-11-22

申请号：US14633011

申请日：2015-02-26

Applicant: QUALCOMM Incorporated

Inventor： Vladimir Machkaoutsan ,  Mustafa Badaroglu ,  Jeffrey Junhao Xu ,  Stanley Seungchul Song ,  Choh Fei Yeap

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/06 ,  H01L21/3213 ,  H01L21/321

CPC classification number: H01L21/823828 ,  B82Y10/00 ,  H01L21/321 ,  H01L21/32133 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/0883 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0642 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66803 ,  H01L29/775 ,  H01L29/785

Abstract: An integrated circuit (IC) device may include a first active transistor of a first-type in a first-type region. The first active transistor may have a first-type work function material and a low channel dopant concentration in an active portion of the first active transistor. The IC device may also include a first isolation transistor of the first-type in the first-type region. The second active transistor may have a second-type work function material and the low channel dopant concentration in an active portion of the first isolation transistor. The first isolation transistor may be arranged adjacent to the first active transistor.

Abstract translation: 集成电路（IC）装置可以包括在第一类型区域中的第一类型的第一有源晶体管。 第一有源晶体管可以在第一有源晶体管的有效部分中具有第一类型功函数材料和低通道掺杂剂浓度。 IC器件还可以包括在第一类型区域中的第一类型的第一隔离晶体管。 第二有源晶体管可以具有第二类型功函数材料，并且第一隔离晶体管的有源部分中的低通道掺杂剂浓度。 第一隔离晶体管可以布置成与第一有源晶体管相邻。

公开(公告)号：US20160293475A1

公开(公告)日：2016-10-06

申请号：US14676728

申请日：2015-04-01

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Vidhya Ramachandran ,  Christine Sung-An Hau-Riege ,  John Jianhong Zhu ,  Jeffrey Junhao Xu ,  Jihong Choi ,  Jun Chen ,  Choh Fei Yeap

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/76802 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295

Abstract: Devices and methods to reduce parasitic capacitance are disclosed. A device may include a dielectric layer. The device may include first and second conductive structures and an etch stop layer proximate to the dielectric layer. The etch stop layer may define first and second openings proximate to a region of the dielectric layer between the first and second conductive structures. The device may include first and second airgaps within the region. The device may include a layer of material proximate to (e.g., on, above, or over) the etch stop layer. The layer of material proximate to the etch stop layer may cover the first and second airgaps.

Abstract translation: 公开了减小寄生电容的装置和方法。 器件可以包括电介质层。 该器件可以包括第一和第二导电结构以及靠近电介质层的蚀刻停止层。 蚀刻停止层可以限定靠近第一和第二导电结构之间的电介质层的区域的第一和第二开口。 该装置可以包括区域内的第一和第二气隙。 该装置可以包括靠近蚀刻停止层（例如，在上方，上方或上方）的材料层。 靠近蚀刻停止层的材料层可以覆盖第一和第二气隙。

公开(公告)号：US20160141250A1

公开(公告)日：2016-05-19

申请号：US14660544

申请日：2015-03-17

Applicant: QUALCOMM Incorporated

Inventor： Junjing Bao ,  Jeffrey Junhao Xu ,  John Jianhong Zhu ,  Da Yang ,  Stanley Seungchul Song ,  Choh Fei Yeap

IPC: H01L23/532 ,  H01L21/3205 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/32051 ,  H01L21/76807 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76864 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a dielectric material and an interconnect structure. The semiconductor device further includes a barrier layer positioned between the dielectric material and the interconnect structure. The barrier layer includes two or more metals. Each metal of the two or more metals of the barrier layer is phase segregated from each other metal of the two or more metals.

Abstract translation: 半导体器件包括电介质材料和互连结构。 半导体器件还包括位于介电材料和互连结构之间的阻挡层。 阻挡层包括两种或更多种金属。 阻挡层的两种或更多种金属的每种金属与两种或更多种金属的彼此金属相分离。