公开(公告)号：US5907166A

公开(公告)日：1999-05-25

申请号：US852905

申请日：1997-05-08

申请人： Stephen L. Casper ,  Timothy J. Allen ,  D. Mark Durcan ,  Brian M. Shirley ,  Howard E. Rhodes

发明人： Stephen L. Casper ,  Timothy J. Allen ,  D. Mark Durcan ,  Brian M. Shirley ,  Howard E. Rhodes

IPC分类号： G11C11/401 ,  H01L23/50 ,  H01L23/528 ,  H01L27/10 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072

CPC分类号： H01L23/528 ,  H01L2924/0002 ,  H01L2924/1815

摘要： A 16 megabit (2.sup.24) or greater density single deposition layer metal Dynamic Random Access Memory (DRAM) part is described which allows for a die that fits within an industry-standard 300 ml wide SOJ (Small Outline J-wing) package or a TSOP (Thin, Small Outline Package) with little or no speed loss over previous double metal deposition layered 16 megabit DRAM designs. This is accomplished using a die architecture which allows for a single metal layer signal path, together with the novel use of a lead frame to remove a substantial portion of the power busing from the die, allowing for a smaller, speed-optimized DRAM. The use of a single deposition layer metal results in lower production costs, and shorter production time.

公开(公告)号：US5862072A

公开(公告)日：1999-01-19

申请号：US918498

申请日：1997-08-22

申请人： George B. Raad ,  Stephen L. Casper

发明人： George B. Raad ,  Stephen L. Casper

IPC分类号： G11C7/18 ,  G11C11/4074 ,  G11C11/4097 ,  G11C5/06

CPC分类号： G11C11/4097 ,  G11C11/4074 ,  G11C7/18

摘要： A memory array architecture is described which uses active digit lines at array edges. To maximize array area using active digit lines, a memory array architecture is employed where interior rows of memory cells intersect X columns of memory cells. Rows located along the edge of the array, however, intersect less than X columns of memory cells. Two rows of memory cells located along the edge of the array must be accessed together to form a complete row of X columns.

摘要翻译： 描述了在阵列边缘使用活动数字线的存储器阵列体系结构。 为了使用活动数字线最大化阵列区域，使用存储器阵列架构，其中存储器单元的内部行与存储器单元的X列相交。 然而，沿着阵列边缘的行相交小于X列的存储单元。 必须一起访问位于阵列边缘的两行存储单元，以形成X列的完整行。

公开(公告)号：US5644215A

公开(公告)日：1997-07-01

申请号：US485093

申请日：1995-06-07

申请人： Stephen L. Casper

发明人： Stephen L. Casper

IPC分类号： G11C11/413 ,  G05F1/46 ,  G05F3/20 ,  G05F3/24 ,  G11C5/14 ,  G11C11/408 ,  H02M3/07 ,  G05F1/40 ,  G05F1/44 ,  G05F1/56 ,  G05F1/618

CPC分类号： G05F1/465 ,  G05F3/205 ,  G11C5/147

摘要： A circuit regulates a voltage by controlling a voltage generator. A voltage divider is coupled between the regulated voltage and a supply voltage, and generates a sense voltage. A clamp circuit is coupled to the divider, and reduces the sensitivity between the supply voltage and the regulated voltage by substantially prohibiting the voltage across itself from exceeding a predetermined value A detector circuit is coupled between the divider and the voltage generator, and provides a control signal that deactivates the generator when the sense voltage reaches a first predetermined threshold, and activates the generator when the sense voltage reaches a second predetermined threshold.

摘要翻译： 电路通过控制电压发生器来调节电压。 分压器耦合在调节电压和电源电压之间，并产生感测电压。 钳位电路耦合到分压器，并且通过基本上禁止其自身超过预定值的电压来降低电源电压和调节电压之间的灵敏度。检测器电路耦合在分压器和电压发生器之间，并提供控制 信号，当感测电压达到第一预定阈值时停用发生器，并且当感测电压达到第二预定阈值时激活发生器。

公开(公告)号：US5629843A

公开(公告)日：1997-05-13

申请号：US637008

申请日：1996-04-24

申请人： Daniel R. Loughmiller ,  Stephen L. Casper ,  Greg A. Blodgett

发明人： Daniel R. Loughmiller ,  Stephen L. Casper ,  Greg A. Blodgett

IPC分类号： G11C5/14 ,  H02M3/07 ,  H02M7/25

CPC分类号： H02M3/073 ,  G11C5/145

摘要： A self compensating clamp circuit and a method which limit the voltage of a pump circuit node to a maximum potential. A first pump circuit provides a first pumped potential at a first node which is greater than a supply potential. The first pumped potential is fed to a second pump circuit which generates a second pumped potential at a second node. The clamp circuit is interposed between the first and the second nodes and limits the maximum value of the first pumped potential to the second pumped potential plus a threshold voltage of the clamp circuit.

摘要翻译： 自补偿钳位电路和将泵电路节点的电压限制在最大电位的方法。 第一泵电路在第一节点处提供大于电源电位的第一泵浦电势。 第一泵浦电势被馈送到在第二节点处产生第二泵浦电位的第二泵电路。 钳位电路插入在第一和第二节点之间，并将第一泵浦电位的最大值限制到第二泵浦电位加上钳位电路的阈值电压。

公开(公告)号：US5602785A

公开(公告)日：1997-02-11

申请号：US571532

申请日：1995-12-13

申请人： Stephen L. Casper

发明人： Stephen L. Casper

IPC分类号： G11C11/4091 ,  G11C7/00

CPC分类号： G11C11/4091

摘要： A pull-up circuit for a DRAM P-channel sense amplifier includes an NMOS transistor and a PMOS transistor connected in parallel with each other between a supply voltage and a pull-up node for the sense amplifier. The transistors are connected to a control circuit that turns on the NMOS transistor during a pull-up cycle and turns on the PMOS transistor only during the initial portion of the pull-up cycle.

摘要翻译： 用于DRAM P沟道读出放大器的上拉电路包括在用于读出放大器的电源电压和上拉节点之间彼此并联连接的NMOS晶体管和PMOS晶体管。 晶体管连接到在上拉周期期间导通NMOS晶体管的控制电路，并且仅在上拉周期的初始部分期间导通PMOS晶体管。

公开(公告)号：US5367213A

公开(公告)日：1994-11-22

申请号：US75200

申请日：1993-06-09

申请人： Stephen L. Casper

发明人： Stephen L. Casper

IPC分类号： G11C11/4091 ,  G11C7/06

CPC分类号： G11C11/4091

摘要： This invention is an improved pull-up circuit for P-channel sense amplifiers in dynamic random access memory arrays having non-bootstrapped wordlines. The improved pull-up circuit features a voltage-comparator-controlled P-channel device which couples the power supply bus to a pull-up node for high current flow to the node and to digit lines which are coupled to the node via P-channel isolation devices. During the pull-up cycle, the P-channel device remains "on" as long as a reference voltage is greater than a variable voltage which represents the voltage level on portions of the digit lines farthest from the P-channel sense amplifier. The pull-up circuit also has an N-channel device which couples the power supply node to the pull-up node for maintenance of a desired voltage level equal to V.sub.cc minus the threshold voltage of the N-channel device.

摘要翻译： 本发明是用于具有非引导字线的动态随机存取存储器阵列中的P沟道读出放大器的改进的上拉电路。 改进的上拉电路具有电压比较器控制的P沟道器件，其将电源总线耦合到上拉节点，用于高电流流向节点，以及数字线路，其经由P沟道耦合到节点 隔离装置。 在上拉循环期间，只要参考电压大于表示距离P通道读出放大器最远的数字线的部分上的电压电平的可变电压，则P沟道器件保持“接通”。 上拉电路还具有将电源节点耦合到上拉节点的N沟道器件，用于维持等于Vcc的期望电压电平减去N沟道器件的阈值电压。

公开(公告)号：US5361002A

公开(公告)日：1994-11-01

申请号：US135214

申请日：1993-10-12

申请人： Stephen L. Casper

发明人： Stephen L. Casper

IPC分类号： H03K19/003 ,  H03K3/01

CPC分类号： H03K19/00384

摘要： The CMOS voltage compensating input buffer circuit of the present invention provides a means to stabilize input level trip points and is comprised of a voltage compensating circuit having an input node and an output drive node coupled to an input buffer. The voltage compensating circuit receives its input from a voltage adjusting circuit that follows changes in V.sub.CC while its output drive node is coupled to the series connected CMOS input buffer circuit having an input node and an output node. The buffer's input node receives a signal that VIH/VIL trip points will determine if the output is to be a high or a low and the buffer's output node then couples the resultant level to an output buffer circuit comprised of a CMOS inverter which provides the final output drive. The present invention provides trip point levels corresponding to industry standard VIH/VIL levels to accurately determine the corresponding output with operating voltage supplies (regulated or unregulated) operating between 2 V to 7.5 V.

公开(公告)号：US5220221A

公开(公告)日：1993-06-15

申请号：US847630

申请日：1992-03-06

申请人： Stephen L. Casper

发明人： Stephen L. Casper

IPC分类号： G11C7/06 ,  G11C11/4091 ,  H03K5/24

CPC分类号： H03K5/2472 ,  G11C11/4091 ,  G11C7/06

摘要： A pulldown circuit for a sense amplifier includes an output node for coupling to a common node of one or more sense amplifiers in a DRAM. The drain of an N-channel pulldown transistor is coupled to the output node. Additional pulldown circuitry includes an inverter, a P-channel transistor, and a bias circuit coupled to the supply voltage for providing a gate signal to the gate of the N-channel pulldown transistor. The slope of the gate signal is substantially insensitive to the value of the power supply voltage, thus changing the rate at which the common node is discharged to the enabling ground level. Since the rate of discharge is substantially the same at higher power supply voltages, the instantaneous current is substantially the same, which in turn prevents the internal ground lines from developing an additional undesirable ground voltage increase.

摘要翻译： 用于读出放大器的下拉电路包括用于耦合到DRAM中的一个或多个读出放大器的公共节点的输出节点。 N沟道下拉晶体管的漏极耦合到输出节点。 附加的下拉电路包括反相器，P沟道晶体管和耦合到电源电压的偏置电路，用于向N沟道下拉晶体管的栅极提供栅极信号。 栅极信号的斜率对电源电压的值基本不敏感，从而将公共节点的放电速率改变为使能接地电平。 由于在较高的电源电压下放电速率基本上相同，所以瞬时电流基本相同，这反过来又防止内部接地线产生额外的不期望的接地电压增加。

公开(公告)号：US06954385B2

公开(公告)日：2005-10-11

申请号：US10918386

申请日：2004-08-16

申请人： Stephen L. Casper ,  Kevin Duesman ,  Glen Hush

发明人： Stephen L. Casper ,  Kevin Duesman ,  Glen Hush

IPC分类号： G11C13/00 ,  G11C11/34 ,  G11C13/02 ,  G11C16/28 ,  H01L27/105

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/004 ,  G11C2013/0042 ,  G11C2013/0054 ,  G11C2013/009 ,  G11C2213/79

摘要： A sense circuit for reading a resistance level of a programmable conductor random access memory (PCRAM) cell is provided. A voltage potential difference is introduced across a PCRAM cell by activating an access transistor from a raised rowline voltage. Both a digit line and a digit complement reference line are precharged to a first predetermined voltage. The cell being sensed has the precharged voltage discharged through the resistance of the programmable conductor memory element of the PCRAM cell. A comparison is made of the voltage read at the digit line and at the reference conductor. If the voltage at the digit line is greater than the reference voltage, the cell is read as a high resistance value (e.g., logic HIGH); however, if the voltage measured at the digit line is lower than that of the reference voltage, the cell is read as a low resistance value (e.g., logic LOW).

摘要翻译： 提供了用于读取可编程导体随机存取存储器（PCRAM）单元的电阻电平的读出电路。 通过从升高的行线电压激活存取晶体管，通过PCRAM单元引入电压电位差。 数字线和数位补码参考线都被预充电到第一预定电压。 被感测的电池具有通过PCRAM单元的可编程导体存储元件的电阻放电的预充电电压。 比较在数字线和参考导体读取的电压。 如果数字线上的电压大于参考电压，则将单元读为高电阻值（例如，逻辑高电平）; 然而，如果在数字线处测量的电压低于参考电压的电压，则将该单元读为低电阻值（例如，逻辑低电平）。

公开(公告)号：USRE38685E1

公开(公告)日：2005-01-11

申请号：US10164354

申请日：2002-06-05

申请人： Stephen L. Casper

发明人： Stephen L. Casper

IPC分类号： G11C7/10 ,  G11C11/00 ,  G11C29/02

CPC分类号： G11C7/1069 ,  G11C7/1051 ,  G11C29/02 ,  G11C29/022 ,  G11C29/50012 ,  G11C2207/2254

摘要： A drive circuit includes drive input and output terminals, a supply terminal, a drive transistor, and a drive-control circuit. The drive transistor includes a control terminal, a first transistor terminal coupled to the drive output terminal, and a second transistor terminal coupled to the supply terminal. The drive-control circuit has an input terminal coupled to the drive input terminal and has an output terminal coupled to the control terminal of the drive transistor. The drive-control circuit generates on the control terminal of the drive transistor a signal level that changes at a first rate during a first time period and at a second higher rate during a second time period following the first time period. As a result, when used as a data-output driver, one can adjust the first and second rates and time periods such that the drive circuit meets both the 50-ohm and 50 pf falling-slew-rate ranges specified in the Intel® PC-100 specification.