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48 条记录 (耗时 0.019 秒)

    Method and apparatus for self-timed data ordering for multi-data rate memories and system incorporating same
    1.
    发明授权
    Method and apparatus for self-timed data ordering for multi-data rate memories and system incorporating same 有权
    用于多数据速率存储器的自定时数据排序的方法和装置以及包含其的系统

    公开(公告)号：US07634623B2

    公开(公告)日：2009-12-15

    申请号：US10652160

    申请日：2003-08-29

    申请人： George B. Raad

    发明人： George B. Raad

    IPC分类号： G06F12/00 ,  G06F13/18 ,  G11C8/00

    CPC分类号： G11C7/1006

    摘要： A self-timed data ordering method and circuit for multi-data rate memories orders a plurality of data words substantially simultaneously retrieved during successive read operations of a memory device. A data word ordering designator is stored from each of the successive read operations and managed in a first-in first-out manner. The data word ordering designator configures ordering circuitry for the desired ordering of the plurality of data words simultaneously retrieved. Following the ordering of the plurality of data words, the properly ordered data words are latched in their desired order for subsequent delivery. Once the properly ordered data words are latched, the ordering circuitry is reconfigured according to the next oldest data word ordering designator. The data word ordering designator retains the pipelined ordering of the corresponding read operations to the corresponding memory banks of the memory device.

    摘要翻译： 用于多数据速率存储器的自定时数据排序方法和电路在存储器件的连续读取操作期间基本上同时检索多个数据字。 从每个连续读取操作存储数据字排序指示符，并以先进先出的方式进行管理。 数据字排序指示符为同时检索的多个数据字的期望顺序配置排序电路。 在多个数据字的排序之后，正确排序的数据字按其所需的顺序锁存以便后续传送。 一旦正确排序的数据字被锁存，则排序电路根据下一个最旧的数据字排序指示符进行重新配置。 数据字排序指示符将相应读操作的流水线排序保留到存储器件的相应存储体。

    DRAM power bus control
    2.
    发明授权
    DRAM power bus control 失效
    DRAM电源总线控制

    公开(公告)号：US07522466B2

    公开(公告)日：2009-04-21

    申请号：US11803444

    申请日：2007-05-14

    申请人： George B Raad

    发明人： George B Raad

    IPC分类号： G11C5/14

    CPC分类号： G11C5/063 ,  G11C5/14 ,  G11C11/406 ,  G11C11/4074 ,  G11C2211/4067 ,  G11C2211/4068

    摘要： A dynamic random access memory (DRAM) is provided that has separate array and peripheral power busing to isolate array noise from peripheral circuits such as delay lock loops during row activations and read/write memory operations. A switch connects the array power bus to another separate power bus for a limited period of time during a DRAM refresh cycle to provide additional current to the DRAM arrays. The switch disconnects the array power bus from the other power bus preferably before the end of the refresh cycle.

    摘要翻译： 提供了一种动态随机存取存储器（DRAM），其具有单独的阵列和外设电源，以便在行激活和读/写存储器操作期间将阵列噪声与诸如延迟锁定环路的外围电路隔离。 在DRAM刷新周期期间，开关将阵列电源总线连接到另一个独立的电源总线一段有限的时间段，以向DRAM阵列提供额外的电流。 该开关优选地在刷新周期结束之前将阵列电源总线与另一个电源总线断开连接。

    Memory architecture and decoder addressing
    4.
    发明授权
    Memory architecture and decoder addressing 有权

    公开(公告)号：US6038159A

    公开(公告)日：2000-03-14

    申请号：US252369

    申请日：1999-02-18

    申请人： George B. Raad

    发明人： George B. Raad

    IPC分类号： G11C5/02

    CPC分类号： G11C5/025

    摘要： A memory architecture includes a matrixed arrangement of memory cell arrays having interstitial separations bounding each memory cell array. The interstitial separations between memory cell arrays include longitudinal streets, carrying row decoders, and latitudinal streets, carrying column decoders that include sense amplifiers. Decoder control circuits are disposed in the intersections of the longitudinal and latitudinal streets. Each decoder control circuit includes drivers for providing addressing or other signals to pairs of adjacent row or column decoders. Each driver provides a signal to more than one decoder, such as to each of the row or column decoders between which the decoder control circuit is interposed. The decoder control circuit requires fewer drivers, which can be staggered or laterally offset to better accommodate magnitude reductions of the interstitial separations between memory cell arrays, thereby increasing storage density.

    Method and memory device for dynamic cell plate sensing with ac equilibrate
    5.
    发明授权
    Method and memory device for dynamic cell plate sensing with ac equilibrate 失效
    用于具有交流平衡的动态电池板感测的方法和存储器件

    公开(公告)号：US5862089A

    公开(公告)日：1999-01-19

    申请号：US911552

    申请日：1997-08-14

    申请人： George B. Raad ,  Stephen L. Casper

    发明人： George B. Raad ,  Stephen L. Casper

    IPC分类号： G11C7/00 ,  G11C11/4074 ,  G11C11/4091 ,  G11C11/4094

    CPC分类号： G11C11/4094 ,  G11C11/4074 ,  G11C11/4091

    摘要： A memory device that uses a dynamic cell plate sensing scheme. The memory device includes an array of word lines and complementary bit line/plate line pairs. A number of memory cells are located at the intersection of selected word lines and bit line/plate line pairs. A sense amplifier is coupled to the complementary bit line/plate line pairs. The memory device also includes an equilibrate circuit that ac equilibrates a complementary bit line/plate line pair at an equilibration voltage between high and low logic levels prior to reading data. The equilibration voltage and the high and low logic levels for the memory cell are chosen such that a fluctuation in the voltage on one of the plate lines does not corrupt data stored in unaccessed memory cells coupled to the same plate line.

    摘要翻译： 一种使用动态单元板感测方案的存储器件。 存储器件包括字线阵列和互补的位线/板线对。 多个存储单元位于选定字线和位线/板线对的交点处。 读出放大器耦合到互补位线/板线对。 存储器件还包括平衡电路，其在读取数据之前在平衡电压之间平衡互补的位线/板线对在高逻辑电平和低逻辑电平之间。 选择存储器单元的平衡电压和高和低逻辑电平，使得一个板线上的电压的波动不会损坏存储在耦合到同一板线的未处理的存储器单元中的数据。

    Fast sense amplifier for small voltage differences
    7.
    发明授权
    Fast sense amplifier for small voltage differences 失效

    公开(公告)号：US5768202A

    公开(公告)日：1998-06-16

    申请号：US800963

    申请日：1997-02-18

    申请人： George B. Raad

    发明人： George B. Raad

    IPC分类号： G11C7/06 ,  G11C11/4091 ,  G11C7/00

    CPC分类号： G11C7/065 ,  G11C11/4091

    摘要： A sense amplifier senses a small voltage differential across true and complementary digit lines in a dynamic random access memory (DRAM) integrated circuit. The sensed voltage is further separated and amplified into full logic levels. Activating the P-sense amplifier before the N-sense amplifier speeds sensing. The P-sense amplifier control signal is capacitively coupled to each of the true and complementary digit lines. The P-sense amplifier further increases the more positive digit line to the power supply voltage V.sub.cc. The other digit line is at a voltage more positive than its equilibration voltage, speeding conduction of a subsequently activated N-sense amplifier, particularly for low values of V.sub.cc, in which the threshold voltages of the NFETs in the N-sense amplifier are close to the equilibration voltage. Capacitor elements need not be added to the sense amplifier layout.

    Power-up circuit responsive to supply voltage transients with signal delay
    8.
    发明授权
    Power-up circuit responsive to supply voltage transients with signal delay 失效
    响应于具有信号延迟的电源电压瞬变的上电电路

    公开(公告)号：US5557579A

    公开(公告)日：1996-09-17

    申请号：US494718

    申请日：1995-06-26

    申请人： George B. Raad ,  Stephen L. Casper

    发明人： George B. Raad ,  Stephen L. Casper

    IPC分类号： G11C5/14 ,  G11C5/00

    CPC分类号： G11C5/143

    摘要： A power-up circuit in a computer system drives a memory device such as a dynamic random access memory (DRAM) to an initial condition after the computer system is turned on or reset. The power-up circuit also advantageously drives the memory device into the initial condition upon detecting a transient such as a negative glitch in a supply voltage being provided to the memory device. The power-up circuit includes a voltage level detector which causes a power-up signal to be provided to the memory device upon detecting that the supply voltage is less than a threshold voltage of the memory device which is necessary for the memory device to operate in an operational state. The power-up circuit also includes a delay circuit which causes the power-up signal to be provided to the memory device upon detecting that the supply voltage is beginning to rise from a quiescent voltage and at least until an amount of time determined by an RC time constant of the memory device for the memory device to enter the initial condition has passed. In response to receiving the power-up signal, the memory device enters the initial condition.

    摘要翻译： 计算机系统中的上电电路在计算机系统接通或复位之后将诸如动态随机存取存储器（DRAM）的存储器件驱动到初始状态。 在检测到诸如提供给存储器件的电源电压中的负毛刺之类的瞬态时，上电电路还有利地将存储器件驱动到初始状态。 上电电路包括电压电平检测器，其在检测到电源电压小于存储器件操作所需的存储器件的阈值电压时，将上电信号提供给存储器件 操作状态。 上电电路还包括延迟电路，其在检测到电源电压从静态电压开始上升时使得上电信号被提供给存储器件，并且至少直到由RC确定的时间量 用于存储器件的存储器件的时间常数进入初始条件已经过去了。 响应于接收到上电信号，存储器件进入初始状态。

    DRAM power bus control
    10.
    发明授权
    DRAM power bus control 失效

    公开(公告)号：US07391666B2

    公开(公告)日：2008-06-24

    申请号：US11803443

    申请日：2007-05-14

    申请人： George B Raad

    发明人： George B Raad

    IPC分类号： G11C5/14

    CPC分类号： G11C5/063 ,  G11C5/14 ,  G11C11/406 ,  G11C11/4074 ,  G11C2211/4067 ,  G11C2211/4068

    摘要： A dynamic random access memory (DRAM) is provided that has separate array and peripheral power busing to isolate array noise from peripheral circuits such as delay lock loops during row activations and read/write memory operations. A switch connects the array power bus to another separate power bus for a limited period of time during a DRAM refresh cycle to provide additional current to the DRAM arrays. The switch disconnects the array power bus from the other power bus preferably before the end of the refresh cycle.