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    ADJUSTMENT CIRCUIT FOR PARTITIONED MEMORY BLOCK
    11.
    发明申请
    ADJUSTMENT CIRCUIT FOR PARTITIONED MEMORY BLOCK 审中-公开

    公开(公告)号：US20180308554A1

    公开(公告)日：2018-10-25

    申请号：US16023393

    申请日：2018-06-29

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Der CHIH ,  Hung-Chang YU ,  Ku-Feng LIN

    IPC: G11C16/28 ,  G11C16/08

    CPC classification number: G11C16/28 ,  G11C16/08

    Abstract: The present disclosure describes an adjustment circuit that can be used, for example, in a memory system with partitioned memory blocks. The adjustment circuit can include a controller circuit, a timer circuit, and a temperature adaptive reference (TAR) generator. The controller circuit can be configured to output a control signal that indicates a memory type (e.g., code memory or data memory) associated with a partitioned memory block. The timer circuit can be configured to output a timing signal for a read memory operation based on the control signal. And, the TAR generator can be configured to adjust a verify reference current for a verify memory operation based on temperature, where the verify reference current is set based on the control signal.

    RRAM-BASED AUTHENTICATION CIRCUIT
    12.
    发明申请
    RRAM-BASED AUTHENTICATION CIRCUIT 有权

    公开(公告)号：US20180151224A1

    公开(公告)日：2018-05-31

    申请号：US15435082

    申请日：2017-02-16

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Der CHIH ,  Shih-Lien Linus Lu ,  Yu-Der Chih

    IPC: G11C13/00

    CPC classification number: G11C13/0059 ,  G11C13/004 ,  G11C13/0069

    Abstract: A memory device includes a memory array comprising a plurality of bits, wherein each bit comprises two memory cells each having a variable resistance; a formation circuit, coupled to the plurality of bits, and configured to cause a first memory cell of a first bit to be at a low resistance state; and an authentication circuit, coupled to the plurality of bits, configured to designate a logical state to the first memory cell of the first bit and use the logical state of the first memory cell of the first bit to generate a physically unclonable function (PUF) signature.

    MEMORY DEVICE AND REFERENCE CIRCUIT THEREOF
    13.
    发明申请
    MEMORY DEVICE AND REFERENCE CIRCUIT THEREOF 审中-公开

    公开(公告)号：US20170330608A1

    公开(公告)日：2017-11-16

    申请号：US15667600

    申请日：2017-08-02

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Chia-Fu LEE ,  Yu-Der CHIH ,  Hon-Jarn LIN ,  Yi-Chun SHIH

    IPC: G11C11/16

    CPC classification number: G11C11/1673 ,  G11C7/062 ,  G11C7/22 ,  G11C11/161 ,  G11C13/004 ,  G11C2013/0045 ,  G11C2013/0054 ,  G11C2013/0057 ,  G11C2207/063

    Abstract: A device includes memory cells, a reference circuit, and a sensing unit. The reference circuit includes a first reference switch, a second reference switch, and reference storage units. The first reference switch is turned on when a reference word line is activated. The second reference switch is turned on when the reference word line is activated. The reference storage units include a first reference storage unit and a second reference storage unit. The first reference storage unit generates a first signal having a first logic state when the first reference switch is turned on. The second reference storage unit generates a second signal having a second logic state when the second reference switch is turned on. The sensing unit determines a logic state of the bit data of one of the memory cells according to the first signal and the second signal.

    CIRCUITS AND METHODS FOR COMPENSATING A MISMATCH IN A SENSE AMPLIFIER
    17.
    发明公开
    CIRCUITS AND METHODS FOR COMPENSATING A MISMATCH IN A SENSE AMPLIFIER 审中-公开

    公开(公告)号：US20230386528A1

    公开(公告)日：2023-11-30

    申请号：US18232768

    申请日：2023-08-10

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ku-Feng LIN ,  Yu-Der CHIH ,  Yi-Chun SHIH ,  Chia-Fu LEE

    IPC: G11C7/06 ,  G11C7/08 ,  G11C13/00 ,  G11C11/14

    CPC classification number: G11C7/065 ,  G11C7/08 ,  G11C13/004 ,  G11C11/14 ,  H01L27/10

    Abstract: Circuits and methods for compensating mismatches in sense amplifiers are disclosed. In one example, a circuit is disclosed. The circuit includes: a first branch, a second branch, a first plurality of trimming transistors and a second plurality of trimming transistors. The first branch comprises a first transistor, a second transistor, and a first node coupled between the first transistor and the second transistor. The second branch comprises a third transistor, a fourth transistor, and a second node coupled between the third transistor and the fourth transistor. The first node is coupled to respective gates of the third transistor and the fourth transistor. The second node is coupled to respective gates of the first transistor and the second transistor. The first plurality of trimming transistors is coupled to the second transistor in parallel. The second plurality of trimming transistors is coupled to the fourth transistor in parallel.

    RESISTIVE RANDOM ACCESS MEMORY DEVICE
    19.
    发明申请
    RESISTIVE RANDOM ACCESS MEMORY DEVICE 有权

    公开(公告)号：US20230113903A1

    公开(公告)日：2023-04-13

    申请号：US18080696

    申请日：2022-12-13

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Der CHIH ,  Chung-Cheng Chou ,  Wen-Ting Chu

    IPC: G11C13/00

    Abstract: A memory architecture includes: a plurality of cell arrays each of which comprises a plurality of bit cells, wherein each of bit cells of the plurality of cell arrays uses a respective variable resistance dielectric layer to transition between first and second logic states; and a control logic circuit, coupled to the plurality of cell arrays, and configured to cause a first information bit to be written into respective bit cells of a pair of cell arrays as an original logic state of the first information bit and a logically complementary logic state of the first information bit, wherein the respective variable resistance dielectric layers are formed by using a same recipe of deposition equipment and have different diameters.

    NOVEL MEMORY DEVICE
    20.
    发明申请
    NOVEL MEMORY DEVICE 有权

    公开(公告)号：US20210090672A1

    公开(公告)日：2021-03-25

    申请号：US17111323

    申请日：2020-12-03

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Der CHIH ,  Chien-Yin LIU ,  Yi-Chun SHIH

    IPC: G11C16/34 ,  G11C16/26 ,  G11C16/10

    Abstract: A circuit includes: writing a plurality of data words, each of which has a plurality of data bits, into respective bit cells of a memory device; in response to determining that not all the data bits of the plurality of data words are correctly written into the respective bit cells of the memory device, grouping the plurality of data words as a plurality of data word sets; and simultaneously rewriting a subset of data bits that were not correctly written into the respective bit cells of the memory device, wherein the subset of the data bits are contained in a respective one of the plurality of data word sets.

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