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    STRUCTURE FOR MULTIPLE SENSE AMPLIFIERS OF MEMORY DEVICE
    1.
    发明申请
    STRUCTURE FOR MULTIPLE SENSE AMPLIFIERS OF MEMORY DEVICE 有权

    公开(公告)号：US20220358973A1

    公开(公告)日：2022-11-10

    申请号：US17874973

    申请日：2022-07-27

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Ku-Feng LIN ,  Hiroki NOGUCHI

    IPC: G11C7/06 ,  G11C13/00 ,  G11C11/16

    Abstract: A memory device includes a plurality of sense amplifiers, a plurality of memory cells, a plurality of data lines, a plurality of reference cells, and a connection line. The memory cells are coupled to a plurality of first inputs of the plurality of sense amplifiers respectively. The data lines are coupled to a plurality of second inputs of the plurality of sense amplifiers respectively. The reference cells are arranged in a plurality of columns respectively and coupled to the plurality of data line respectively. Each of the plurality of reference cells includes a plurality of resistive elements. The connection line is coupled to the plurality of data lines. In a read mode, one of the sense amplifiers is configured to access the plurality of resistive elements arranged in at least one of the plurality of columns.

    CIRCUITS AND METHODS FOR COMPENSATING A MISMATCH IN A SENSE AMPLIFIER
    2.
    发明公开
    CIRCUITS AND METHODS FOR COMPENSATING A MISMATCH IN A SENSE AMPLIFIER 审中-公开

    公开(公告)号：US20230386528A1

    公开(公告)日：2023-11-30

    申请号：US18232768

    申请日：2023-08-10

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ku-Feng LIN ,  Yu-Der CHIH ,  Yi-Chun SHIH ,  Chia-Fu LEE

    IPC: G11C7/06 ,  G11C7/08 ,  G11C13/00 ,  G11C11/14

    CPC classification number: G11C7/065 ,  G11C7/08 ,  G11C13/004 ,  G11C11/14 ,  H01L27/10

    Abstract: Circuits and methods for compensating mismatches in sense amplifiers are disclosed. In one example, a circuit is disclosed. The circuit includes: a first branch, a second branch, a first plurality of trimming transistors and a second plurality of trimming transistors. The first branch comprises a first transistor, a second transistor, and a first node coupled between the first transistor and the second transistor. The second branch comprises a third transistor, a fourth transistor, and a second node coupled between the third transistor and the fourth transistor. The first node is coupled to respective gates of the third transistor and the fourth transistor. The second node is coupled to respective gates of the first transistor and the second transistor. The first plurality of trimming transistors is coupled to the second transistor in parallel. The second plurality of trimming transistors is coupled to the fourth transistor in parallel.

    ADAPTIVE WORD-LINE BOOST DRIVER
    3.
    发明申请
    ADAPTIVE WORD-LINE BOOST DRIVER 有权
    自适应字幕升压驱动器

    公开(公告)号：US20140071750A1

    公开(公告)日：2014-03-13

    申请号：US13706380

    申请日：2012-12-06

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Ku-Feng LIN ,  Hung-Chang YU ,  Kai-Chun LIN

    IPC: G11C16/08 ,  G11C16/06

    CPC classification number: G11C16/08 ,  G11C8/08 ,  G11C11/4085 ,  G11C16/06

    Abstract: A word line driver circuit includes a first transistor having its gate coupled to a first node configured to receive a word line select signal. A second transistor has its gate coupled to the first node and a drain coupled to a drain of the first transistor at a second node that is coupled to a word line. A word line assist control circuit is coupled to the first node, to the word line, and to a gate of a third transistor. The word line assist control circuit is configured to turn on or turn off the third transistor to adjust a voltage of the word line.

    Abstract translation: 字线驱动器电路包括第一晶体管，其第一晶体管的栅极耦合到被配置为接收字线选择信号的第一节点。 第二晶体管具有耦合到第一节点的栅极，以及耦合到字线的第二节点处耦合到第一晶体管的漏极的漏极。 字线辅助控制电路耦合到第一节点，字线和第三晶体管的栅极。 字线辅助控制电路被配置为接通或关断第三晶体管以调节字线的电压。

    RESISTIVE MEMORY ARRAY AND FABRICATING METHOD THEREOF
    4.
    发明申请
    RESISTIVE MEMORY ARRAY AND FABRICATING METHOD THEREOF 有权
    电阻记忆阵列及其制作方法

    公开(公告)号：US20150144860A1

    公开(公告)日：2015-05-28

    申请号：US14087782

    申请日：2013-11-22

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Ku-Feng LIN ,  Hung-Chang YU ,  Kai-Chun LIN ,  Yue-Der CHIH

    IPC: H01L27/24 ,  H01L45/00

    CPC classification number: H01L27/2463 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53257 ,  H01L25/18 ,  H01L27/088 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1641 ,  H01L45/1683

    Abstract: The present disclosure provides a method of fabricating a resistive memory array. In one embodiment, a method of fabricating a resistive memory array includes forming a plurality of insulators and a conductive structure on a first substrate, performing a resistor-forming process to transform the insulators into a plurality of resistors, polishing the conductive structure to expose a plurality of contact points respectively electrically connected to the resistors, providing a second substrate having a plurality of transistors and a plurality of interconnect pads, bonding respectively the interconnect pads and the contact points, and removing the first substrate from the resistors and the conductive structure.

    Abstract translation: 本公开提供一种制造电阻式存储器阵列的方法。 在一个实施例中，制造电阻式存储器阵列的方法包括在第一衬底上形成多个绝缘体和导电结构，执行电阻器形成工艺以将绝缘体变换成多个电阻器，抛光导电结构以暴露出 分别电连接到所述电阻器的多个接触点，提供具有多个晶体管和多个互连焊盘的第二基板，分别结合所述互连焊盘和所述接触点，以及从所述电阻器和所述导电结构移除所述第一基板。

    ACCOMMODATING BALANCE OF BIT LINE AND SOURCE LINE RESISTANCES IN MAGNETORESISTIVE RANDOM ACCESS MEMORY
    5.
    发明申请
    ACCOMMODATING BALANCE OF BIT LINE AND SOURCE LINE RESISTANCES IN MAGNETORESISTIVE RANDOM ACCESS MEMORY 有权
    磁条随机访问存储器中位线和源线电阻的平衡

    公开(公告)号：US20140211549A1

    公开(公告)日：2014-07-31

    申请号：US13753569

    申请日：2013-01-30

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Kai-Chun LIN ,  Hung-Chang YU ,  Ku-Feng LIN ,  Yue-Der CHIH

    IPC: G11C11/16

    CPC classification number: G11C11/1675 ,  G11C7/12 ,  G11C7/14 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1697

    Abstract: A memory has magnetic tunnel junction elements with different resistances in different logic states, for bit positions in memory words accessed by a word line signal coupling each bit cell in the addressed word between a bit line and source line for that bit position. The bit lines and source lines are longer and shorter at different word line locations, causing a resistance body effect. A clamping transistor couples the bit line to a sensing circuit when reading, applying a current through the bit cell and producing a read voltage compared by the sensing circuit to a reference such as a comparable voltage from a reference bit cell circuit having a similar structure. A drive control varies an input to the switching transistor as a function of the word line location, e.g., by word line address, to offset the different bit and source line resistances.

    Abstract translation: 存储器具有在不同逻辑状态下具有不同电阻的磁性隧道结元件，对于通过字线信号访问的位线信号中的位位置，该位线信号将该位位置的位线和源极线之间的寻址字中的每个位单元耦合。 位线和源极线在不同的字线位置越来越短，从而产生电阻体效应。 当读取电流时，钳位晶体管将位线耦合到感测电路，通过位单元施加电流，并将由感测电路比较的读取电压产生为诸如具有类似结构的参考位单元电路的可比电压的参考。 驱动控制通过例如字线地址改变作为字线位置的函数的开关晶体管的输入，以偏移不同的位和源极线电阻。

    CIRCUITS AND METHODS FOR COMPENSATING A MISMATCH IN A SENSE AMPLIFIER
    6.
    发明申请
    CIRCUITS AND METHODS FOR COMPENSATING A MISMATCH IN A SENSE AMPLIFIER 有权

    公开(公告)号：US20210142832A1

    公开(公告)日：2021-05-13

    申请号：US17156383

    申请日：2021-01-22

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ku-Feng LIN ,  Yu-Der Chih ,  Yi-Chun Shih ,  Chia-Fu Lee

    IPC: G11C7/06 ,  G11C7/08 ,  G11C13/00 ,  G11C11/14

    Abstract: Circuits and methods for compensating mismatches in sense amplifiers are disclosed. In one example, a circuit is disclosed. The circuit includes: a first branch, a second branch, a first plurality of trimming transistors and a second plurality of trimming transistors. The first branch comprises a first transistor, a second transistor, and a first node coupled between the first transistor and the second transistor. The second branch comprises a third transistor, a fourth transistor, and a second node coupled between the third transistor and the fourth transistor. The first node is coupled to respective gates of the third transistor and the fourth transistor. The second node is coupled to respective gates of the first transistor and the second transistor. The first plurality of trimming transistors is coupled to the second transistor in parallel. The second plurality of trimming transistors is coupled to the fourth transistor in parallel.

    STRUCTURE FOR MULTIPLE SENSE AMPLIFIERS OF MEMORY DEVICE
    10.
    发明申请
    STRUCTURE FOR MULTIPLE SENSE AMPLIFIERS OF MEMORY DEVICE 有权

    公开(公告)号：US20240395290A1

    公开(公告)日：2024-11-28

    申请号：US18790426

    申请日：2024-07-31

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Ku-Feng LIN ,  Hiroki NOGUCHI

    IPC: G11C7/06 ,  G11C11/16 ,  G11C13/00

    Abstract: A memory device includes a plurality of sense amplifiers, a plurality of memory cells, a plurality of data lines, a plurality of reference cells, and a connection line. The memory cells are coupled to a plurality of first inputs of the plurality of sense amplifiers respectively. The data lines are coupled to a plurality of second inputs of the plurality of sense amplifiers respectively. The reference cells are arranged in a plurality of columns respectively and coupled to the plurality of data line respectively. Each of the plurality of reference cells includes a plurality of resistive elements. The connection line is coupled to the plurality of data lines. In a read mode, one of the sense amplifiers is configured to access the plurality of resistive elements arranged in at least one of the plurality of columns.

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