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    CIRCUITS AND METHODS FOR COMPENSATING A MISMATCH IN A SENSE AMPLIFIER
    4.
    发明公开
    CIRCUITS AND METHODS FOR COMPENSATING A MISMATCH IN A SENSE AMPLIFIER 审中-公开

    公开(公告)号：US20240363152A1

    公开(公告)日：2024-10-31

    申请号：US18767858

    申请日：2024-07-09

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ku-Feng LIN ,  Yu-Der CHIH ,  Yi-Chun SHIH ,  Chia-Fu LEE

    IPC: G11C7/06 ,  G11C7/08 ,  G11C11/14 ,  G11C13/00 ,  H01L27/10

    CPC classification number: G11C7/065 ,  G11C7/08 ,  G11C11/14 ,  G11C13/004 ,  H01L27/10

    Abstract: Circuits and methods for compensating mismatches in sense amplifiers are disclosed. In one example, a circuit is disclosed. The circuit includes: a first branch, a second branch, a first plurality of trimming transistors and a second plurality of trimming transistors. The first branch comprises a first transistor, a second transistor, and a first node coupled between the first transistor and the second transistor. The second branch comprises a third transistor, a fourth transistor, and a second node coupled between the third transistor and the fourth transistor. The first node is coupled to respective gates of the third transistor and the fourth transistor. The second node is coupled to respective gates of the first transistor and the second transistor. The first plurality of trimming transistors is coupled to the second transistor in parallel. The second plurality of trimming transistors is coupled to the fourth transistor in parallel.

    CIRCUITS AND METHODS FOR COMPENSATING A MISMATCH IN A SENSE AMPLIFIER
    5.
    发明申请
    CIRCUITS AND METHODS FOR COMPENSATING A MISMATCH IN A SENSE AMPLIFIER 有权

    公开(公告)号：US20220262409A1

    公开(公告)日：2022-08-18

    申请号：US17737734

    申请日：2022-05-05

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ku-Feng LIN ,  Yu-Der CHIH ,  Yi-Chun SHIH ,  Chia-Fu LEE

    IPC: G11C7/06 ,  G11C7/08 ,  G11C13/00 ,  G11C11/14

    Abstract: Circuits and methods for compensating mismatches in sense amplifiers are disclosed. In one example, a circuit is disclosed. The circuit includes: a first branch, a second branch, a first plurality of trimming transistors and a second plurality of trimming transistors. The first branch comprises a first transistor, a second transistor, and a first node coupled between the first transistor and the second transistor. The second branch comprises a third transistor, a fourth transistor, and a second node coupled between the third transistor and the fourth transistor. The first node is coupled to respective gates of the third transistor and the fourth transistor. The second node is coupled to respective gates of the first transistor and the second transistor. The first plurality of trimming transistors is coupled to the second transistor in parallel. The second plurality of trimming transistors is coupled to the fourth transistor in parallel.

    MEMORY DEVICE AND REFERENCE CIRCUIT THEREOF
    6.
    发明申请
    MEMORY DEVICE AND REFERENCE CIRCUIT THEREOF 审中-公开

    公开(公告)号：US20170330608A1

    公开(公告)日：2017-11-16

    申请号：US15667600

    申请日：2017-08-02

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Chia-Fu LEE ,  Yu-Der CHIH ,  Hon-Jarn LIN ,  Yi-Chun SHIH

    IPC: G11C11/16

    CPC classification number: G11C11/1673 ,  G11C7/062 ,  G11C7/22 ,  G11C11/161 ,  G11C13/004 ,  G11C2013/0045 ,  G11C2013/0054 ,  G11C2013/0057 ,  G11C2207/063

    Abstract: A device includes memory cells, a reference circuit, and a sensing unit. The reference circuit includes a first reference switch, a second reference switch, and reference storage units. The first reference switch is turned on when a reference word line is activated. The second reference switch is turned on when the reference word line is activated. The reference storage units include a first reference storage unit and a second reference storage unit. The first reference storage unit generates a first signal having a first logic state when the first reference switch is turned on. The second reference storage unit generates a second signal having a second logic state when the second reference switch is turned on. The sensing unit determines a logic state of the bit data of one of the memory cells according to the first signal and the second signal.

    CIRCUITS AND METHODS FOR COMPENSATING A MISMATCH IN A SENSE AMPLIFIER
    8.
    发明公开
    CIRCUITS AND METHODS FOR COMPENSATING A MISMATCH IN A SENSE AMPLIFIER 审中-公开

    公开(公告)号：US20230386528A1

    公开(公告)日：2023-11-30

    申请号：US18232768

    申请日：2023-08-10

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ku-Feng LIN ,  Yu-Der CHIH ,  Yi-Chun SHIH ,  Chia-Fu LEE

    IPC: G11C7/06 ,  G11C7/08 ,  G11C13/00 ,  G11C11/14

    CPC classification number: G11C7/065 ,  G11C7/08 ,  G11C13/004 ,  G11C11/14 ,  H01L27/10

    Abstract: Circuits and methods for compensating mismatches in sense amplifiers are disclosed. In one example, a circuit is disclosed. The circuit includes: a first branch, a second branch, a first plurality of trimming transistors and a second plurality of trimming transistors. The first branch comprises a first transistor, a second transistor, and a first node coupled between the first transistor and the second transistor. The second branch comprises a third transistor, a fourth transistor, and a second node coupled between the third transistor and the fourth transistor. The first node is coupled to respective gates of the third transistor and the fourth transistor. The second node is coupled to respective gates of the first transistor and the second transistor. The first plurality of trimming transistors is coupled to the second transistor in parallel. The second plurality of trimming transistors is coupled to the fourth transistor in parallel.

    NOVEL RESISTIVE RANDOM ACCESS MEMORY DEVICE
    9.
    发明申请
    NOVEL RESISTIVE RANDOM ACCESS MEMORY DEVICE 有权

    公开(公告)号：US20210183444A1

    公开(公告)日：2021-06-17

    申请号：US17180283

    申请日：2021-02-19

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chia-Fu LEE ,  Yu-Der Chih

    IPC: G11C13/00

    Abstract: A memory device includes: a memory bit cell; a write circuit, coupled to the memory bit cell, and configured to use a first voltage to transition the memory bit cell to a first logic state by changing a respective resistance state of the memory bit cell, and compare a first current flowing through the memory bit cell with a first reference current; and a control logic circuit, coupled to the write circuit, and configured to determine whether the first logic state is successfully written into the memory bit cell based on a read-out logic state of the memory bit cell and the comparison between the first current and first reference current.

    NOVEL RESISTIVE RANDOM ACCESS MEMORY DEVICE
    10.
    发明申请
    NOVEL RESISTIVE RANDOM ACCESS MEMORY DEVICE 审中-公开

    公开(公告)号：US20200027506A1

    公开(公告)日：2020-01-23

    申请号：US16588383

    申请日：2019-09-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chia-Fu LEE ,  Yu-Der CHIH

    IPC: G11C13/00

    Abstract: A memory device includes: a memory bit cell; a write circuit, coupled to the memory bit cell, and configured to use a first voltage to transition the memory bit cell to a first logic state by changing a respective resistance state of the memory bit cell, and compare a first current flowing through the memory bit cell with a first reference current; and a control logic circuit, coupled to the write circuit, and configured to determine whether the first logic state is successfully written into the memory bit cell based on a read-out logic state of the memory bit cell and the comparison between the first current and first reference current.

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