公开(公告)号：US10700032B2

公开(公告)日：2020-06-30

申请号：US16532162

申请日：2019-08-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shuo-Mao Chen ,  Der-Chyang Yeh ,  Li-Hsien Huang

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L23/525 ,  H01L21/56 ,  H01L23/538 ,  H01L21/768

Abstract: An embodiment is a device comprising a substrate, a metal pad over the substrate, and a passivation layer comprising a portion over the metal pad. The device further comprises a metal pillar over and electrically coupled to the metal pad, and a passive device comprising a first portion at a same level as the metal pillar, wherein the first portion of the passive device is formed of a same material as the metal pillar.

公开(公告)号：US10535597B2

公开(公告)日：2020-01-14

申请号：US15851174

申请日：2017-12-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Shuo-Mao Chen ,  Feng-Cheng Hsu ,  Shin-Puu Jeng

IPC: H01L23/498 ,  H01L25/18 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/14 ,  H01L23/538

Abstract: The present disclosure provides a semiconductor package device, which includes an interposer die. The interposer die includes a semiconductor substrate and a plurality of through-silicon-vias (TSVs) extending through the semiconductor substrate. The semiconductor package device also includes a semiconductor die spaced apart from the interposer die, a first redistribution layer disposed on a first side of the interposer die and electrically coupling the interposer die with the semiconductor die, and a second redistribution layer on a second side of the interposer die opposite the first side.

公开(公告)号：US10050024B2

公开(公告)日：2018-08-14

申请号：US15370865

申请日：2016-12-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Jui-Pin Hung ,  Feng-Cheng Hsu ,  Shuo-Mao Chen ,  Shin-Puu Jeng

IPC: H01L23/48 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00

Abstract: The present disclosure provides a semiconductor package, including a first layer, a second layer, and a conductive array. The first layer includes a packaged die having a carrier surface and a molding surface, and a first die structure in proximity to the carrier surface. An active region of the first die structure is electrically coupled to the packaged die through a solder. The second layer includes a second die structure, the second die structure being connected to the active region of the first die structure by a first redistributed layer (RDL). The conductive array is connected to an active region of the second die structure by a second RDL. The present disclosure also provides a method for manufacturing the aforesaid semiconductor package.

公开(公告)号：US20180197755A1

公开(公告)日：2018-07-12

申请号：US15911893

申请日：2018-03-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Feng-Cheng Hsu ,  Shuo-Mao Chen ,  Jui-Pin Hung ,  Shin-Puu Jeng

IPC: H01L21/56 ,  H01L23/00 ,  H01L21/78 ,  H01L23/31

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/00 ,  H01L24/02 ,  H01L24/19 ,  H01L24/83 ,  H01L24/97 ,  H01L25/00 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2224/81 ,  H01L2224/83

Abstract: An embodiment device package includes a first die, a second die, and a molding compound extending along sidewalls of the first die and the second die. The package further includes redistribution layers (RDLs) extending laterally past edges of the first die and the second die. The RDLs include an input/output (I/O) contact electrically connected to the first die and the second die, and the I/O contact is exposed at a sidewall of the device package substantially perpendicular to a surface of the molding compound opposite the RDLs.

公开(公告)号：US20180082966A1

公开(公告)日：2018-03-22

申请号：US15823110

申请日：2017-11-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shuo-Mao Chen ,  Der-Chyang Yeh ,  Li-Hsien Huang

IPC: H01L23/00 ,  H01L23/522 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/538 ,  H01L23/525

CPC classification number: H01L24/11 ,  H01L21/56 ,  H01L21/568 ,  H01L21/76801 ,  H01L23/3107 ,  H01L23/3135 ,  H01L23/3192 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/525 ,  H01L23/5389 ,  H01L2924/0002 ,  H01L2924/12042 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00

Abstract: An embodiment is a device comprising a substrate, a metal pad over the substrate, and a passivation layer comprising a portion over the metal pad. The device further comprises a metal pillar over and electrically coupled to the metal pad, and a passive device comprising a first portion at a same level as the metal pillar, wherein the first portion of the passive device is formed of a same material as the metal pillar.

公开(公告)号：US20170229322A1

公开(公告)日：2017-08-10

申请号：US15225083

申请日：2016-08-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Feng-Cheng Hsu ,  Shuo-Mao Chen ,  Jui-Pin Hung ,  Shin-Puu Jeng

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L21/78

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/19 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2224/81 ,  H01L2224/83

Abstract: An embodiment device package includes a first die, a second die, and a molding compound extending along sidewalls of the first die and the second die. The package further includes redistribution layers (RDLs) extending laterally past edges of the first die and the second die. The RDLs include an input/output (I/O) contact electrically connected to the first die and the second die, and the I/O contact is exposed at a sidewall of the device package substantially perpendicular to a surface of the molding compound opposite the RDLs.

公开(公告)号：US20150255447A1

公开(公告)日：2015-09-10

申请号：US14720154

申请日：2015-05-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jui-Pin Hung ,  Jing-Cheng Lin ,  Po-Hao Tsai ,  Yi-Jou Lin ,  Shuo-Mao Chen ,  Chiung-Han Yeh ,  Der-Chyang Yeh

IPC: H01L25/00 ,  H01L25/18 ,  H01L21/82 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L21/76843 ,  H01L21/82 ,  H01L23/28 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/528 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/19 ,  H01L24/73 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/83 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/82

Abstract: An interconnect structure and a method of forming an interconnect structure are provided. The interconnect structure is formed over a carrier substrate, upon which a die may also be attached. Upon removal of the carrier substrate and singulation, a first package is formed. A second package may be attached to the first package, wherein the second package may be electrically coupled to through vias formed in the first package.

Abstract translation: 提供互连结构和形成互连结构的方法。 互连结构形成在载体基板上，模具也可以附着在载体基板上。 在移除载体衬底和单片化时，形成第一封装。 第二封装可以附接到第一封装，其中第二封装可以电耦合到形成在第一封装中的通孔。

公开(公告)号：US20140252646A1

公开(公告)日：2014-09-11

申请号：US13787547

申请日：2013-03-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jui-Pin Hung ,  Jing-Cheng Lin ,  Po-Hao Tsai ,  Yi-Jou Lin ,  Shuo-Mao Chen ,  Chiung-Han Yeh ,  Der-Chyang Yeh

IPC: H01L23/48 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L21/76843 ,  H01L21/82 ,  H01L23/28 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/528 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/19 ,  H01L24/73 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/83 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/82

Abstract: An interconnect structure and a method of forming an interconnect structure are provided. The interconnect structure is formed over a carrier substrate, upon which a die may also be attached. Upon removal of the carrier substrate and singulation, a first package is formed. A second package may be attached to the first package, wherein the second package may be electrically coupled to through vias formed in the first package.

Abstract translation: 提供互连结构和形成互连结构的方法。 互连结构形成在载体基板上，模具也可以附着在载体基板上。 在移除载体衬底和单片化时，形成第一封装。 第二封装可以附接到第一封装，其中第二封装可以电耦合到形成在第一封装中的通孔。

公开(公告)号：US20240387472A1

公开(公告)日：2024-11-21

申请号：US18789630

申请日：2024-07-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Kuei Hsu ,  Feng-Cheng Hsu ,  Ming-Chih Yew ,  Po-Yao Lin ,  Shuo-Mao Chen ,  Shin-Puu Jeng

IPC: H01L25/065 ,  H01L21/50 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538

Abstract: A semiconductor package includes a semiconductor die, a redistribution circuit structure, a supporting structure and a protective layer. The redistribution circuit structure is located on and electrically coupled to the semiconductor die. The supporting structure is located on an outer surface of the redistribution circuit structure, wherein the supporting structure is overlapped with at least a part of the semiconductor die or has a sidewall substantially aligned with a sidewall of the semiconductor die in a vertical projection on the redistribution circuit structure along a stacking direction of the redistribution circuit structure and the supporting structure. The protective layer is located on the supporting structure, wherein the supporting structure is sandwiched between the protective layer and the redistribution circuit structure.

公开(公告)号：US12046548B2

公开(公告)日：2024-07-23

申请号：US18307091

申请日：2023-04-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shin-Puu Jeng ,  Po-Hao Tsai ,  Po-Yao Chuang ,  Feng-Cheng Hsu ,  Shuo-Mao Chen ,  Techi Wong

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/52 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/053 ,  H01L25/00 ,  H01L25/10 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/52 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/053 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/27 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/96 ,  H01L25/105 ,  H01L25/50 ,  H01L21/561 ,  H01L23/3128 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2224/0401 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/26175 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/83191 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/15311 ,  H01L2224/97 ,  H01L2224/81 ,  H01L2224/97 ,  H01L2224/83

Abstract: A chip package is provided. The chip package includes a substrate structure. The substrate structure includes a redistribution structure having a conductive pad. The substrate structure includes a first insulating layer under the redistribution structure. The substrate structure includes a conductive via structure passing through the first insulating layer. The conductive via structure is under and electrically connected with the conductive pad. The substrate structure includes a second insulating layer disposed between the redistribution structure and the first insulating layer. The chip package includes a first chip over the redistribution structure and electrically connected to the conductive via structure through the redistribution structure. The chip package includes a second chip under the substrate structure.