公开(公告)号：US09362278B1

公开(公告)日：2016-06-07

申请号：US14585110

申请日：2014-12-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Hsiang Huang ,  Da-Wen Lin

IPC: H01L31/062 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/324 ,  H01L21/265

CPC classification number: H01L29/7847 ,  H01L21/26506 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A device comprises a first semiconductor fin over a substrate, a second semiconductor fin over the substrate, wherein the first semiconductor fin and the second semiconductor fin are separated by a first isolation region, a first drain/source region coupled to the first semiconductor fin and the second semiconductor fin and a first dislocation plane underlying the first isolation region, wherein the first dislocation plane extends in a first direction in parallel with a longitudinal axis of the first semiconductor fin.

Abstract translation: 一种器件包括在衬底上的第一半导体鳍片，在衬底上的第二半导体鳍片，其中第一半导体鳍片和第二半导体鳍片由第一隔离区域隔开，第一漏极/源极区域耦合到第一半导体鳍片，以及 所述第二半导体鳍片和位于所述第一隔离区域下方的第一位错平面，其中所述第一位错平面在与所述第一半导体鳍片的纵向轴线平行的第一方向上延伸。

公开(公告)号：US08895383B2

公开(公告)日：2014-11-25

申请号：US13863963

申请日：2013-04-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tung Ying Lee ,  Li-Wen Weng ,  Chien-Tai Chan ,  Da-Wen Lin ,  Hsien-Chin Lin

IPC: H01L21/8238 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/785

Abstract: A system and method for manufacturing multiple-gate semiconductor devices is disclosed. An embodiment comprises multiple fins, wherein intra-fin isolation regions extend into the substrate less than inter-fin isolation regions. Regions of the multiple fins not covered by the gate stack are removed and source/drain regions are formed from the substrate so as to avoid the formation of voids between the fins in the source/drain region.

Abstract translation: 公开了一种用于制造多栅极半导体器件的系统和方法。 一个实施例包括多个散热片，其中散热片内隔离区域延伸到小于鳍间隔离区域的衬底内。 去除未被栅极堆叠覆盖的多个鳍片的区域，并且从衬底形成源极/漏极区域，以避免在源极/漏极区域中的鳍片之间形成空隙。

公开(公告)号：US20130280876A1

公开(公告)日：2013-10-24

申请号：US13918682

申请日：2013-06-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun Hsiung Tsai ,  Chien-Tai Chan ,  Mao-Rong Yeh ,  Da-Wen Lin

IPC: H01L29/66

CPC classification number: H01L29/66803 ,  H01L21/2236 ,  H01L21/2254 ,  H01L21/26526 ,  H01L21/26586

Abstract: A method of forming an integrated circuit includes providing a semiconductor wafer including a semiconductor fin dispatched on a surface of the semiconductor wafer; forming a dopant-rich layer having an impurity on a top surface and sidewalls of the semiconductor fin, wherein the impurity is of n-type or p-type; performing a knock-on implantation to drive the impurity into the semiconductor fin; and removing the dopant-rich layer.

Abstract translation: 一种形成集成电路的方法包括提供半导体晶片，该半导体晶片包括在半导体晶片的表面上分配的半导体鳍; 在所述半导体鳍片的顶表面和侧壁上形成具有杂质的富掺杂层，其中所述杂质为n型或p型; 执行敲击植入以将杂质驱动到半导体鳍片中; 并除去富含掺杂剂的层。

公开(公告)号：US20230137528A1

公开(公告)日：2023-05-04

申请号：US17832587

申请日：2022-06-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Yuan Wu ,  Min Jiao ,  Da-Wen Lin

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/06 ,  H01L27/11

Abstract: The present disclosure provides a method that includes providing a substrate including a first circuit region and a second circuit region; forming a semiconductor stack on the substrate, wherein the semiconductor stack includes first semiconductor layers of a first composition and second semiconductor layers of a second composition alternatively stacked on the substrate; performing a first patterning process to the semiconductor stack and the substrate to form first trenches having a first depth; and performing a second patterning process to the semiconductor stack and the substrate, thereby forming second trenches of a second depth in the first circuit region and third trenches of a third depth in the second circuit region, the third depth being less than the second depth.

公开(公告)号：US20230015372A1

公开(公告)日：2023-01-19

申请号：US17736898

申请日：2022-05-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Yuan Wu ,  Da-Wen Lin ,  Yi-Ting Fu ,  Hsu-Chieh Cheng ,  Min Jiao

IPC: H01L21/28 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/66

Abstract: A method includes forming a fin protruding from a substrate, forming a first dielectric feature adjacent to the fin over the substrate, forming a cladding layer over the fin and the first dielectric feature, and removing a portion of the cladding layer to form an opening. The opening exposes the first dielectric feature. The method further includes forming a second dielectric feature adjacent to the cladding layer, the second dielectric feature filling the opening, forming a dummy gate stack over the fin and the second dielectric feature, forming source/drain (S/D) features in the fin adjacent to the dummy gate stack, and replacing the dummy gate stack and the cladding layer with a metal gate stack. The second dielectric feature divides the metal gate stack.

公开(公告)号：US10153344B2

公开(公告)日：2018-12-11

申请号：US15707886

申请日：2017-09-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun Hsiung Tsai ,  Wei-Yuan Lu ,  Chien-Tai Chan ,  Wei-Yang Lee ,  Da-Wen Lin

IPC: H01L21/336 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/02 ,  H01L29/16 ,  H01L29/32 ,  H01L29/04 ,  H01L29/06 ,  H01L29/165

Abstract: Embodiments of mechanisms for forming dislocations in source and drain regions of finFET devices are provided. The mechanisms involve recessing fins and removing the dielectric material in the isolation structures neighboring fins to increase epitaxial regions for dislocation formation. The mechanisms also involve performing a pre-amorphous implantation (PAI) process either before or after the epitaxial growth in the recessed source and drain regions. An anneal process after the PAI process enables consistent growth of the dislocations in the source and drain regions. The dislocations in the source and drain regions (or stressor regions) can form consistently to produce targeted strain in the source and drain regions to improve carrier mobility and device performance for NMOS devices.

公开(公告)号：US09768277B2

公开(公告)日：2017-09-19

申请号：US14815375

申请日：2015-07-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Lung Cheng ,  Da-Wen Lin ,  Yen-Chun Lin

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/51 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/324 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/165

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/511 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7847 ,  H01L29/7848

Abstract: Various methods include providing a substrate, forming a projection extending upwardly from the substrate, the projection having a channel region therein, and forming a gate structure engaging the projection adjacent to the channel region, the gate structure having spaced first and second conductive layers and a strain-inducing conductive layer disposed between the first and second conductive layers. The method also includes forming epitaxial growths on portions of the projection at each side of the gate structure, the epitaxial growths imparting a first strain to the channel region, and imparting a second strain to the channel region, including performing at least one stress memorization technique on the gate structure such that the strain-inducing conductive layer imparts the second strain to the channel region, and removing the capping layer, wherein the imparting the second strain is carried out in a manner that imparts tensile strain to the channel region.

公开(公告)号：US09620386B2

公开(公告)日：2017-04-11

申请号：US14444706

申请日：2014-07-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chun Hsiung Tsai ,  Xiong-Fei Yu ,  Yu-Lien Huang ,  Da-Wen Lin

IPC: H01L21/28 ,  H01L29/40 ,  H01L21/324 ,  H01L29/51 ,  H01L29/66 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L21/324 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28185 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7833

Abstract: A method of fabricating a gate structure includes depositing a high dielectric constant (high-k) dielectric layer over a substrate. The method further includes performing a multi-stage preheat high-temperature anneal. Performing the multi-stage preheat high-temperature anneal includes performing a first stage preheat at a temperature in a range from about 400° C. to about 600° C., performing a second stage preheat at a temperature in a range from about 700° C. to about 900° C., and performing a high temperature anneal at a peak temperature in a range from 875° C. to about 1200° C.

公开(公告)号：US20160268429A1

公开(公告)日：2016-09-15

申请号：US15161723

申请日：2016-05-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Hsiang Huang ,  Da-Wen Lin

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/324 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L29/7847 ,  H01L21/26506 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A method comprises forming a first fin and a second fin over a substrate, wherein the first fin and the second fin are separated by a trench, applying a first pre-amorphous implantation (PAI) process to the substrate and forming a first PAI region underlying the trench as a result of the first PAI process, depositing a first tensile film layer on sidewalls and a bottom of the trench, converting the first PAI region into a first dislocation plane underlying the trench using a first anneal process and forming an isolation region over the first dislocation plane.

Abstract translation: 一种方法包括在衬底上形成第一鳍片和第二鳍片，其中所述第一鳍片和所述第二鳍片由沟槽分开，对所述衬底施加第一预非晶注入（PAI）工艺并形成第一PAI区域的底层 作为第一PAI工艺的结果的沟槽，在沟槽的侧壁和底部上沉积第一拉伸膜层，使用第一退火工艺将第一PAI区域转换成沟槽下面的第一位错平面，并形成隔离区域 第一位错平面。

公开(公告)号：US20160204229A1

公开(公告)日：2016-07-14

申请号：US15076061

申请日：2016-03-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun Hsiung Tsai ,  Wei-Yuan Lu ,  Chien-Tai Chan ,  Wei-Yang Lee ,  Da-Wen Lin

IPC: H01L29/66 ,  H01L29/16 ,  H01L29/165 ,  H01L29/78 ,  H01L29/08 ,  H01L21/02

CPC classification number: H01L29/0847 ,  H01L21/02521 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/32 ,  H01L29/41766 ,  H01L29/66795 ,  H01L29/7847 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7855 ,  H01L29/7856

Abstract: Embodiments of mechanisms for forming dislocations in source and drain regions of finFET devices are provided. The mechanisms involve recessing fins and removing the dielectric material in the isolation structures neighboring fins to increase epitaxial regions for dislocation formation. The mechanisms also involve performing a pre-amorphous implantation (PAI) process either before or after the epitaxial growth in the recessed source and drain regions. An anneal process after the PAI process enables consistent growth of the dislocations in the source and drain regions. The dislocations in the source and drain regions (or stressor regions) can form consistently to produce targeted strain in the source and drain regions to improve carrier mobility and device performance for NMOS devices.