公开(公告)号：US11171134B2

公开(公告)日：2021-11-09

申请号：US16721283

申请日：2019-12-19

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Xiong-Fei Yu ,  Chun-Yuan Chou ,  Kuang-Yuan Hsu ,  Da-Yuan Lee ,  Jeff J. Xu

IPC分类号： H01L27/092 ,  H01L29/66 ,  H01L21/285 ,  H01L21/8238 ,  H01L21/768 ,  H01L21/28 ,  H01L29/51 ,  H01L29/49 ,  H01L21/3205 ,  H01L29/78 ,  H01L29/165

摘要： A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.

公开(公告)号：US10374055B2

公开(公告)日：2019-08-06

申请号：US14303045

申请日：2014-06-12

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Cheng-Hao Hou ,  Wei-Yang Lee ,  Xiong-Fei Yu ,  Kuang-Yuan Hsu

IPC分类号： H01L29/51 ,  H01L29/49 ,  H01L21/28 ,  H01L29/78

摘要： A semiconductor device including a substrate having a source region, a drain region, and a channel region disposed between the source region and the drain region. Additionally, the semiconductor device includes a high-k dielectric layer formed over the channel region, an n-metal formed over the high-k dielectric layer and a barrier layer formed between the high-k dielectric layer and the n-metal, the barrier layer including a layer of annealed silicon.

公开(公告)号：US10269921B2

公开(公告)日：2019-04-23

申请号：US15357675

申请日：2016-11-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Cheng Chen ,  Liang-Yin Chen ,  Xiong-Fei Yu ,  Syun-Ming Jang ,  Hui-Cheng Chang ,  Meng-Shu Lin

IPC分类号： H01L29/51 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H01L29/165

摘要： An embodiment fin field-effect-transistor (finFET) includes a semiconductor fin comprising a channel region and a gate oxide on a sidewall and a top surface of the channel region. The gate oxide includes a thinnest portion having a first thickness and a thickest portion having a second thickness different than the first thickness. A difference between the first thickness and the second thickness is less than a maximum thickness variation, and the maximum thickness variation is in accordance with an operating voltage of the finFET.

公开(公告)号：US20180145143A1

公开(公告)日：2018-05-24

申请号：US15357675

申请日：2016-11-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Cheng Chen ,  Liang-Yin Chen ,  Xiong-Fei Yu ,  Syun-Ming Jang ,  Hui-Cheng Chang ,  Meng-Shu Lin

IPC分类号： H01L29/423 ,  H01L21/8234 ,  H01L29/51 ,  H01L27/088 ,  H01L21/28 ,  H01L21/02 ,  H01L29/78

CPC分类号： H01L29/518 ,  H01L21/0214 ,  H01L21/0223 ,  H01L21/02247 ,  H01L21/02255 ,  H01L21/28202 ,  H01L21/823431 ,  H01L21/823462 ,  H01L27/0886 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7851 ,  H01L29/7856

摘要： An embodiment fin field-effect-transistor (finFET) includes a semiconductor fin comprising a channel region and a gate oxide on a sidewall and a top surface of the channel region. The gate oxide includes a thinnest portion having a first thickness and a thickest portion having a second thickness different than the first thickness. A difference between the first thickness and the second thickness is less than a maximum thickness variation, and the maximum thickness variation is in accordance with an operating voltage of the finFET.

公开(公告)号：US20160379831A1

公开(公告)日：2016-12-29

申请号：US15220909

申请日：2016-07-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yee-Chia Yeo ,  Chih Chieh Yeh ,  Chih-Hsin Ko ,  Cheng-Hsien Wu ,  Liang-Yin Chen ,  Xiong-Fei Yu ,  Yen-Ming Chen ,  Chan-Lon Yang

IPC分类号： H01L21/28 ,  H01L29/78 ,  H01L29/66 ,  H01L29/51

CPC分类号： H01L21/28185 ,  H01L21/26513 ,  H01L21/28088 ,  H01L21/28238 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7851 ,  H01L29/78651 ,  H01L29/78684 ,  H01L29/78696

摘要： A method includes forming a silicon cap layer on a semiconductor fin, forming an interfacial layer over the silicon cap layer, forming a high-k gate dielectric over the interfacial layer, and forming a scavenging metal layer over the high-k gate dielectric. An anneal is then performed on the silicon cap layer, the interfacial layer, the high-k gate dielectric, and the scavenging metal layer. A filling metal is deposited over the high-k gate dielectric.

摘要翻译： 一种方法包括在半导体鳍片上形成硅覆盖层，在硅覆盖层上形成界面层，在界面层上形成高k栅极电介质，并在高k栅极电介质上形成清除金属层。 然后在硅覆盖层，界面层，高k栅极电介质和扫气金属层上进行退火。 填充金属沉积在高k栅极电介质上。

公开(公告)号：US09515188B2

公开(公告)日：2016-12-06

申请号：US14579955

申请日：2014-12-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Cheng Chen ,  Meng-Shu Lin ,  Liang-Yin Chen ,  Xiong-Fei Yu ,  Hui-Cheng Chang ,  Syun-Ming Jang

IPC分类号： H01L29/78 ,  H01L29/08 ,  H01L29/51 ,  H01L29/66 ,  H01L21/8234

CPC分类号： H01L29/7856 ,  H01L21/823431 ,  H01L21/823462 ,  H01L29/0886 ,  H01L29/518 ,  H01L29/66795

摘要： An embodiment fin field-effect-transistor (finFET) includes a semiconductor fin comprising a channel region and a gate oxide on a sidewall and a top surface of the channel region. The gate oxide includes a thinnest portion having a first thickness and a thickest portion having a second thickness different than the first thickness. A difference between the first thickness and the second thickness is less than a maximum thickness variation, and the maximum thickness variation is in accordance with an operating voltage of the finFET.

摘要翻译： 实施例鳍片场效应晶体管（finFET）包括半导体鳍片，其包括沟道区域和侧壁上的栅极氧化物以及沟道区域的顶表面。 栅极氧化物包括具有第一厚度的最薄部分和具有不同于第一厚度的第二厚度的最厚部分。 第一厚度和第二厚度之间的差小于最大厚度变化，并且最大厚度变化与finFET的工作电压相一致。

公开(公告)号：US09263546B2

公开(公告)日：2016-02-16

申请号：US14585802

申请日：2014-12-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Wei-Yang Lee ,  Xiong-Fei Yu ,  Da-Yuan Lee ,  Kuang-Yuan Hsu

IPC分类号： H01L29/04 ,  H01L29/10 ,  H01L29/66 ,  H01L29/423 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/51

CPC分类号： H01L29/66477 ,  H01L21/28185 ,  H01L21/823857 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/66545

摘要： A method of making a semiconductor device, the method includes forming an active region in a substrate. The method further includes forming a first gate structure over the active region, where the forming the first gate structure includes forming a first interfacial layer. An entirety of a top surface of the first interfacial layer is a curved convex surface. Furthermore, the method includes forming a first high-k dielectric over the first interfacial layer. Additionally, the method includes forming a first gate electrode over a first portion of the first high-k dielectric and surrounded by a second portion of the first high-k dielectric.

摘要翻译： 一种制造半导体器件的方法，所述方法包括在衬底中形成有源区。 该方法还包括在有源区上形成第一栅极结构，其中形成第一栅极结构包括形成第一界面层。 第一界面层的整个顶面是弯曲的凸面。 此外，该方法包括在第一界面层上形成第一高k电介质。 另外，该方法包括在第一高k电介质的第一部分上形成第一栅极，并被第一高k电介质的第二部分包围。

公开(公告)号：US20150017796A1

公开(公告)日：2015-01-15

申请号：US14497639

申请日：2014-09-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Xiong-Fei Yu ,  Chun-Yuan Chou ,  Da-Yuan Lee ,  Kuang-Yuan Hsu ,  Jeff J. Xu

IPC分类号： H01L29/49 ,  H01L21/285 ,  H01L21/768 ,  H01L21/3205 ,  H01L29/66 ,  H01L29/51

CPC分类号： H01L27/092 ,  H01L21/28088 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/32051 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823842 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7848

摘要： A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.

摘要翻译： 公开了一种具有金属栅极的半导体器件。 具有金属栅极的示例性半导体器件包括半导体衬底，半导体衬底上的源极和漏极特征，半导体衬底上的栅极堆叠并且设置在源极和漏极特征之间。 所述栅堆叠包括形成在所述半导体衬底上的HK电介质层，形成在所述HK电介质层的顶部上的金属化合物的多个势垒层，其中每个所述阻挡层具有不同的化学组成; 以及沉积在所述多个阻挡层上的一叠金属栅极层。

公开(公告)号：US10964543B2

公开(公告)日：2021-03-30

申请号：US16673555

申请日：2019-11-04

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tsung-Da Lin ,  Che-Hao Chang ,  Cheng-Hao Hou ,  Xiong-Fei Yu

IPC分类号： H01L21/28 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49

摘要： Embodiments disclosed herein relate to formation of a gate structure of a device, such as in a replacement gate process, and the device formed thereby. In an embodiment, a method includes conformally forming a gate dielectric layer on a fin extending from a substrate and along sidewalls of gate spacers over the fin, conformally depositing a dummy layer over the gate dielectric layer during a deposition process using a silicon-containing precursor and a dopant gas containing fluorine, deuterium, or a combination thereof, the dummy layer as deposited comprising a dopant of fluorine, deuterium, or a combination thereof, performing a thermal process to drive the dopant from the dummy layer into the gate dielectric layer, removing the dummy layer, and forming one or more metal-containing layers over the gate dielectric layer.

公开(公告)号：US10263091B2

公开(公告)日：2019-04-16

申请号：US15379067

申请日：2016-12-14

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yee-Chia Yeo ,  Chih Chieh Yeh ,  Chih-Hsin Ko ,  Cheng-Hsien Wu ,  Liang-Yin Chen ,  Xiong-Fei Yu ,  Yen-Ming Chen ,  Chan-Lon Yang

IPC分类号： H01L29/76 ,  H01L29/49 ,  H01L29/10 ,  H01L29/66 ,  H01L29/165 ,  H01L21/28 ,  H01L29/51 ,  H01L29/78 ,  H01L21/265 ,  H01L21/324 ,  H01L29/06 ,  H01L29/08 ,  H01L29/161 ,  H01L29/423 ,  H01L29/786

摘要： A method includes forming a silicon cap layer on a semiconductor fin, forming an interfacial layer over the silicon cap layer, forming a high-k gate dielectric over the interfacial layer, and forming a scavenging metal layer over the high-k gate dielectric. An anneal is then performed on the silicon cap layer, the interfacial layer, the high-k gate dielectric, and the scavenging metal layer. A filling metal is deposited over the high-k gate dielectric.