公开(公告)号：US20160163684A1

公开(公告)日：2016-06-09

申请号：US15042268

申请日：2016-02-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Bruce C.S. Chou ,  Chen-Jong Wang ,  Ping-Yin Liu ,  Jung-Kuo Tu ,  Tsung-Te Chou ,  Xin-Hua Huang ,  Hsun-Chung Kuang ,  Lan-Lin Chao ,  Chia-Shiung Tsai ,  Xiaomeng Chen

IPC: H01L25/00 ,  H01L21/308 ,  H01L23/00 ,  H01L21/764

CPC classification number: H01L24/80 ,  H01L21/3081 ,  H01L21/764 ,  H01L23/498 ,  H01L23/5226 ,  H01L23/53204 ,  H01L23/53228 ,  H01L23/5329 ,  H01L23/53295 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/09 ,  H01L24/83 ,  H01L24/93 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/03845 ,  H01L2224/05554 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/0601 ,  H01L2224/08147 ,  H01L2224/0901 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06524 ,  H01L2924/00011 ,  H01L2924/01322 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/81805

Abstract: A package component includes a surface dielectric layer including a planar top surface, a metal pad in the surface dielectric layer and including a second planar top surface level with the planar top surface, and an air trench on a side of the metal pad. The sidewall of the metal pad is exposed to the air trench.

Abstract translation: 封装部件包括表面电介质层，其包括平面顶表面，表面电介质层中的金属焊盘，并且包括具有平坦顶表面的第二平面顶表面水平面和在金属焊盘一侧的空气沟槽。 金属垫的侧壁暴露于空气沟槽。

公开(公告)号：US20150344297A1

公开(公告)日：2015-12-03

申请号：US14692238

申请日：2015-04-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Bruce C.S. Chou ,  Jung-Kuo Tu ,  Chen-Chih Fan

IPC: B81C1/00

CPC classification number: B81C1/00158 ,  B81C1/00301 ,  G01P15/125 ,  H01G5/18 ,  H01L28/60

Abstract: A device includes a semiconductor substrate, and a capacitive sensor having a back-plate, wherein the back-plate forms a first capacitor plate of the capacitive sensor. The back-plate is a portion of the semiconductor substrate. A conductive membrane is spaced apart from the semiconductor substrate by an air-gap. A capacitance of the capacitive sensor is configured to change in response to a movement of the polysilicon membrane.

Abstract translation: 一种器件包括半导体衬底和具有背板的电容传感器，其中所述背板形成所述电容式传感器的第一电容器板。 背板是半导体衬底的一部分。 导电膜通过气隙与半导体衬底间隔开。 电容传感器的电容被配置成响应于多晶硅膜的移动而改变。

公开(公告)号：US20140151823A1

公开(公告)日：2014-06-05

申请号：US13953238

申请日：2013-07-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Bruce C.S. Chou

IPC: B81B3/00

CPC classification number: B81B3/0018 ,  B81B2203/0307 ,  B81B2203/04 ,  B81B2207/07 ,  B81C1/00476 ,  B81C1/00801 ,  B81C2201/0109 ,  H01L24/13 ,  H01L24/80 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/13009 ,  H01L2224/13138 ,  H01L2224/80011 ,  H01L2224/80012 ,  H01L2224/80013 ,  H01L2224/80031 ,  H01L2224/80047 ,  H01L2224/8009 ,  H01L2224/80092 ,  H01L2224/80931 ,  H01L2224/81002 ,  H01L2224/81007 ,  H01L2224/811 ,  H01L2224/9202 ,  H01L2924/1461 ,  H01L21/76898 ,  H01L2924/01014 ,  H01L2924/00

Abstract: The present invention provides a MEMS structure comprising confined sacrificial oxide layer and a bonded Si layer. Polysilicon stack is used to fill aligned oxide openings and MEMS vias on the sacrificial layer and the bonded Si layer respectively. To increase the design flexibility, some conductive polysilicon layer can be further deployed underneath the bonded Si layer to form the functional sensing electrodes or wiring interconnects. The MEMS structure can be further bonded to a metallic layer on top of the Si layer and the polysilicon stack.

Abstract translation: 本发明提供一种MEMS结构，其包括受限的牺牲氧化物层和结合的Si层。 多晶硅叠层用于在牺牲层和结合的Si层上分别填充对准的氧化物开口和MEMS通孔。 为了增加设计灵活性，可以将一些导电多晶硅层进一步布置在结合的Si层下面以形成功能感测电极或布线互连。 MEMS结构可以进一步结合到Si层和多晶硅叠层顶部的金属层。

公开(公告)号：US20170330979A1

公开(公告)日：2017-11-16

申请号：US15664588

申请日：2017-07-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo-Chin Huang ,  Tzu-Jui Wang ,  Szu-Ying Chen ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Bruce C.S. Chou ,  Jung-Kuo Tu ,  Cheng-Chieh Hsieh

IPC: H01L31/024 ,  H01L27/146 ,  H01L31/02

CPC classification number: H01L27/1469 ,  H01L27/14618 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14645 ,  H01L27/14689 ,  H01L31/02019 ,  H01L31/024 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A system and method for blocking heat from reaching an image sensor in a three dimensional stack with a semiconductor device. In an embodiment a heat sink is formed in a back end of line process either on the semiconductor device or else on the image sensor itself when the image sensor is in a backside illuminated configuration. The heat sink may be a grid in either a single layer or in two layers, a zig-zag pattern, or in an interleaved fingers configuration.

公开(公告)号：US20160009551A1

公开(公告)日：2016-01-14

申请号：US14860505

申请日：2015-09-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chang-Chia Chang ,  Chen-Chih Fan ,  Bruce C.S. Chou

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00269 ,  B81B3/0018 ,  B81B3/0067 ,  B81B3/007 ,  B81B7/00 ,  B81B7/0006 ,  B81B7/0016 ,  B81B7/0029 ,  B81B7/0041 ,  B81B7/0051 ,  B81B7/0058 ,  B81B2201/0228 ,  B81B2201/0235 ,  B81B2201/025 ,  B81B2207/07 ,  B81B2207/096 ,  B81C1/00 ,  B81C1/00293 ,  B81C1/00325 ,  B81C2203/0118

Abstract: A microelectromechanical system (MEMS) device may include a MEMS structure above a first substrate. The MEMS structure comprising a central static element, a movable element, and an outer static element. A portion of bonding material between the central static element and the first substrate. A second substrate above the MEMS structure, with a portion of a dielectric layer between the central static element and the second substrate. A supporting post comprises the portion of bonding material, the central static element, and the portion of dielectric material.

公开(公告)号：US20150262958A1

公开(公告)日：2015-09-17

申请号：US14724694

申请日：2015-05-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shang-Yun Hou ,  Sao-Ling Chiu ,  Ping-Kang Huang ,  Wen Hsin Wei ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Bruce C.S. Chou

IPC: H01L23/00 ,  H01L23/522 ,  H01L21/56 ,  H01L23/31 ,  H01L21/306 ,  H01L21/304

CPC classification number: H01L24/17 ,  H01L21/304 ,  H01L21/30604 ,  H01L21/44 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/49811 ,  H01L23/522 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/09 ,  H01L24/11 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/0382 ,  H01L2224/0401 ,  H01L2224/05026 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/1182 ,  H01L2224/13 ,  H01L2224/16113 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2924/0002 ,  H01L2924/181 ,  H01L2924/00

Abstract: Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a method of forming a semiconductor device, the method comprising forming a conductive pad in a first substrate, forming an interconnecting structure over the conductive pad and the first substrate, the interconnecting structure comprising a plurality of metal layers disposed in a plurality of dielectric layers, bonding a die to a first side of the interconnecting structure, and etching the first substrate from a second side of the interconnecting structure, the etching exposing a portion of the conductive pad.

Abstract translation: 本公开的实施例包括半导体器件和形成半导体器件的方法。 一个实施例是一种形成半导体器件的方法，所述方法包括在第一衬底中形成导电焊盘，在导电焊盘和第一衬底之上形成互连结构，所述互连结构包括多个设置在多个 介电层，将管芯连接到互连结构的第一侧，并且从互连结构的第二侧蚀刻第一衬底，蚀刻暴露导电焊盘的一部分。

公开(公告)号：US20150162220A1

公开(公告)日：2015-06-11

申请号：US14621567

申请日：2015-02-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Bruce C.S. Chou ,  Chih-Hsien Lin ,  Hsiang-Tai Lu ,  Jung-Kuo Tu ,  Tung-Hung Hsieh ,  Chen-Hua Lin ,  Mingo Liu

IPC: H01L21/56 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L21/56 ,  H01L21/486 ,  H01L21/563 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/3135 ,  H01L23/3185 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13184 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/2101 ,  H01L2224/214 ,  H01L2224/215 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81193 ,  H01L2224/81424 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/81895 ,  H01L2224/82101 ,  H01L2224/83104 ,  H01L2224/85 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/1531 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2924/014 ,  H01L2924/01029 ,  H01L2924/01013 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01074 ,  H01L2924/01028 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A semiconductor device includes a first die having a first active surface and a first backside surface opposite the first active surface, a second die having a second active surface and a second backside surface opposite the second active surface, and an interposer, the first active surface of the first die being electrically coupled to a first side of the interposer, the second active surface of the second die being electrically coupled to a second side of the interposer. The semiconductor device also includes a first connector over the interposer, a first encapsulating material surrounding the second die, the first encapsulating material having a first surface over the interposer, and a via electrically coupling the first connector and the interposer. A first end of the via is substantially coplanar with the first surface of the first encapsulating material.

Abstract translation: 半导体器件包括具有第一有源表面和与第一有源表面相对的第一背面的第一管芯，具有第二有源表面和与第二有源表面相对的第二背面的第二管芯，以及插入件，第一有源表面 所述第一管芯电耦合到所述插入件的第一侧，所述第二管芯的所述第二有源表面电连接到所述插入件的第二侧。 半导体器件还包括位于插入器上的第一连接器，围绕第二管芯的第一封装材料，第一封装材料具有位于插入件上的第一表面，以及电连接第一连接器和插入件的通孔。 通孔的第一端与第一封装材料的第一表面基本共面。

公开(公告)号：US20140264698A1

公开(公告)日：2014-09-18

申请号：US13929661

申请日：2013-06-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo-Chin Huang ,  Tzu-Jui Wang ,  Szu-Ying Chen ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Bruce C.S. Chou ,  Jung-Kuo Tu ,  Cheng-Chieh Hsieh

IPC: H01L31/024 ,  H01L31/02

CPC classification number: H01L31/024 ,  H01L27/14618 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14645 ,  H01L27/14689 ,  H01L27/1469 ,  H01L31/02019 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A system and method for blocking heat from reaching an image sensor in a three dimensional stack with a semiconductor device. In an embodiment a heat sink is formed in a back end of line process either on the semiconductor device or else on the image sensor itself when the image sensor is in a backside illuminated configuration. The heat sink may be a grid in either a single layer or in two layers, a zig-zag pattern, or in an interleaved fingers configuration.

Abstract translation: 一种用于阻挡热量到达具有半导体器件的三维堆叠中的图像传感器的系统和方法。 在一个实施例中，当图像传感器处于背面照明配置时，在半导体器件上或者在图像传感器本身上的线后处理中形成散热器。 散热器可以是单层或两层，锯齿形图案或交错手指配置中的网格。