公开(公告)号：US10332890B2

公开(公告)日：2019-06-25

申请号：US15653198

申请日：2017-07-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok Lee ,  Chan-Sic Yoon ,  Augustin Hong ,  Keunnam Kim ,  Dongoh Kim ,  Bong-Soo Kim ,  Jemin Park ,  Hoin Lee ,  Sungho Jang ,  Kiwook Jung ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L27/24 ,  H01L27/22

Abstract: A method of manufacturing a semiconductor memory device and a semiconductor memory device, the method including providing a substrate that includes a cell array region and a peripheral circuit region; forming a mask pattern that covers the cell array region and exposes the peripheral circuit region; growing a semiconductor layer on the peripheral circuit region exposed by the mask pattern such that the semiconductor layer has a different lattice constant from the substrate; forming a buffer layer that covers the cell array region and exposes the semiconductor layer; forming a conductive layer that covers the buffer layer and the semiconductor layer; and patterning the conductive layer to form conductive lines on the cell array region and to form a gate electrode on the peripheral circuit region.

公开(公告)号：US20240118072A1

公开(公告)日：2024-04-11

申请号：US18215437

申请日：2023-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungho Jang ,  Sangwoo Bae ,  Minhwan Seo ,  Jangwoon Sung ,  Akinori Okubo ,  Seungwoo Lee ,  Jungchul Lee ,  Jaehwang Jung ,  Sangjoon Hong

IPC: G01B11/06 ,  G01B9/02

CPC classification number: G01B11/0608 ,  G01B9/02041 ,  G01B2290/70

Abstract: Provided are a level sensor configured to detect a height level of a substrate, and a substrate processing apparatus including the level sensor. The level sensor includes a measurement light source configured to radiate measurement light toward the substrate, a prism configured to split reflected light of the measurement light into first polarized light and second polarized light and generate a first optical path length difference between the first polarized light and the second polarized light, an optical path length modulator configured to keep constant an optical path length of the first polarized light and periodically change an optical path length of the second polarized light, and a detector configured to detect the first optical path length difference based on an interference signal between the first polarized light and the second polarized light.

公开(公告)号：US20230400404A1

公开(公告)日：2023-12-14

申请号：US18154990

申请日：2023-01-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Garam Choi ,  Wookrae Kim ,  Jinseob Kim ,  Jinyong Kim ,  Sungho Jang ,  Daehoon Han

IPC: G01N21/21 ,  G01B11/24

CPC classification number: G01N21/21 ,  G01B11/24 ,  G01B2210/56

Abstract: A semiconductor measurement apparatus includes an illumination unit including a light source and at least one illumination polarization element, a light receiving unit including at least one light-receiving polarization element disposed on a path of light reflected by a sample, and an image sensor positioned to receive light passing through the at least one light-receiving polarization element and configured to output an original image, and a control unit configured to determine, by processing the original image, a selected critical dimension among critical dimensions of a structure included in a region of the sample. The control unit is configured to obtain a plurality of sample images by selecting regions of the original image in which a peak due to interference appears, to determine a plurality of elements included in a Mueller matrix using the plurality of sample images, and to determine the selected critical dimension based on the plurality of elements.

公开(公告)号：US11676263B2

公开(公告)日：2023-06-13

申请号：US17529403

申请日：2021-11-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Hyub Lee ,  Kyungsik Kang ,  Jeong-Gil Kim ,  Jinyong Kim ,  Hochul Kim ,  Yozo Matsuda ,  Youngduk Suh ,  Seungkoo Lee ,  Sungho Jang ,  Yoojin Jeong

IPC: G06T7/00 ,  G02B5/10 ,  G02B5/20 ,  G02B5/08 ,  G01M11/00 ,  G03F7/20 ,  H04N23/56 ,  G02B27/10 ,  G03F7/00

CPC classification number: G06T7/0004 ,  G01M11/005 ,  G02B5/0816 ,  G02B5/0891 ,  G02B5/10 ,  G02B5/208 ,  G02B27/1013 ,  G03F7/70916 ,  H04N23/56 ,  G06T2207/10152

Abstract: An extreme ultraviolet (EUV) collector inspection apparatus and method capable of precisely inspecting a contamination state of an EUV collector and EUV reflectance in accordance with the contamination state are provided. The EUV collector inspection apparatus includes a light source arranged in front of an EUV collector to be inspected and configured to output light in a visible light (VIS) band from UV rays, an optical device configured to output narrowband light from the light, and a camera configured to perform imaging from an UV band to a VIS band. An image by wavelength of the EUV collector is obtained by using the optical device and the camera and a contamination state of the EUV collector is inspected.

公开(公告)号：US20230078095A1

公开(公告)日：2023-03-16

申请号：US17695062

申请日：2022-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dougyong SUNG ,  Youngdo Kim ,  Byeongsang Kim ,  Yunhwan Kim ,  Jungmo Yang ,  Sejin Oh ,  Sungho Jang

IPC: H01J37/32

Abstract: A plasma etching apparatus includes a housing having a processing space; a support inside the housing, the support configured to support a substrate and including at least one lower electrode; at least one upper electrode facing the at least one lower electrode; a sidewall electrode disposed on a sidewall of the housing; a lower radiofrequency (RF) power source connected to the at least one lower electrode and configured to apply RF power; an upper RF power source connected to the at least one upper electrode and configured to apply RF power; a lower insulator adjacent to the at least one lower electrode; an upper insulator adjacent to the at least one upper electrode; at least one lower detector embedded in the lower insulator; and at least one upper detector embedded in the upper insulator.

公开(公告)号：US09947668B2

公开(公告)日：2018-04-17

申请号：US14591165

申请日：2015-01-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjin Lee ,  Sungho Jang ,  Jiyoung Kim ,  Kang-Uk Kim ,  Chan Min Lee ,  Juyeon Jang

IPC: H01L27/108 ,  H01L21/3213

CPC classification number: H01L27/10885 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/32139 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897

Abstract: Semiconductor devices, and methods for forming the same, include forming a first wiring film and an etching buffer film in a cell array region and a peripheral circuit region of a substrate, and forming a contact hole by selectively etching the etching buffer film and the first wiring film so as to expose an active region of the cell array region and at least a part of a field isolation region adjacent thereto. A bit line contact is formed in the contact hole to be in contact with the active region, and a second wiring film is formed over the substrate. By patterning the second wiring film, the bit line contact, the etching buffer film, and the first wiring film, a bit line is formed in the cell array region and a peripheral gate is formed in the peripheral circuit region.

公开(公告)号：US09305928B2

公开(公告)日：2016-04-05

申请号：US14175076

申请日：2014-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngkuk Kim ,  Ho-Kyun An ,  Jaehyun Yeo ,  Badro Im ,  HanJin Lim ,  Sungho Jang ,  Insang Jeon

IPC: H01L21/8242 ,  H01L27/108 ,  H01L21/8234

CPC classification number: H01L27/10894 ,  H01L21/823412 ,  H01L21/823462 ,  H01L27/10814 ,  H01L27/10861

Abstract: Semiconductor devices having a silicon-germanium channel layer and methods of forming the semiconductor devices are provided. The methods may include forming a silicon-germanium channel layer on a substrate in a peripheral circuit region and sequentially forming a first insulating layer and a second insulating layer on the silicon-germanium channel layer. The methods may also include forming a conductive layer on the substrate, which includes a cell array region and the peripheral circuit region, and patterning the conductive layer to form a conductive line in the cell array region and a gate electrode in the peripheral circuit region. The first insulating layer may be formed at a first temperature and the second insulating layer may be formed at a second temperature higher than the first temperature.

Abstract translation: 提供具有硅 - 锗沟道层的半导体器件和形成半导体器件的方法。 所述方法可以包括在外围电路区域中的衬底上形成硅 - 锗沟道层，并且在硅 - 锗沟道层上依次形成第一绝缘层和第二绝缘层。 该方法还可以包括在衬底上形成导电层，该导电层包括电池阵列区域和外围电路区域，以及图案化导电层以在电池阵列区域中形成导线以及在外围电路区域中形成栅极电极。 第一绝缘层可以在第一温度下形成，并且第二绝缘层可以在高于第一温度的第二温度下形成。

公开(公告)号：US20240274418A1

公开(公告)日：2024-08-15

申请号：US18455949

申请日：2023-08-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungho Jang ,  Protopopov Vladimir ,  Dohoon Kwon ,  Sangki Nam ,  Dougyong Sung ,  Sungwon Cho

IPC: H01J37/32

CPC classification number: H01J37/32972 ,  H01J2237/24564

Abstract: An apparatus for measuring real-time plasma density includes, at least one plasma density measurement sensor in a process chamber, the at least one plasma density measurement sensor being configured to sense a plasma current between a first electrode and a second electrode when plasma is generated, and to generate an optical signal in response to the plasma current, and an optical signal detector on a side surface of the process chamber, the optical signal detector being configured to detect the optical signal from the at least one plasma density measurement sensor.

公开(公告)号：US20240147698A1

公开(公告)日：2024-05-02

申请号：US18368635

申请日：2023-09-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Geonyeop Lee ,  Dongwook Kim ,  Yangdoo Kim ,  Sangki Nam ,  Sangwuk Park ,  Minkyu Suh ,  Dokeun Lee ,  Sungho Jang ,  Jungpyo Hong

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/0335

Abstract: A semiconductor device includes; a lower structure, lower electrodes on the lower structure, wherein each lower electrode includes a first lower electrode and a second lower electrode on the first lower electrode and electrically connected to the first lower electrode, an upper electrode covering the lower electrodes, and a dielectric film between the lower electrodes and the upper electrode, wherein the first lower electrode includes a pillar portion and a protruding portion on the pillar portion, wherein protruding portion has a complex shape that contacts the second lower electrode.

公开(公告)号：US11521977B2

公开(公告)日：2022-12-06

申请号：US17471824

申请日：2021-09-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok Lee ,  Chan-Sic Yoon ,  Augustin Hong ,  Keunnam Kim ,  Dongoh Kim ,  Bong-Soo Kim ,  Jemin Park ,  Hoin Lee ,  Sungho Jang ,  Kiwook Jung ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L27/24 ,  H01L27/22

Abstract: A method of manufacturing a semiconductor memory device and a semiconductor memory device, the method including providing a substrate that includes a cell array region and a peripheral circuit region; forming a mask pattern that covers the cell array region and exposes the peripheral circuit region; growing a semiconductor layer on the peripheral circuit region exposed by the mask pattern such that the semiconductor layer has a different lattice constant from the substrate; forming a buffer layer that covers the cell array region and exposes the semiconductor layer; forming a conductive layer that covers the buffer layer and the semiconductor layer; and patterning the conductive layer to form conductive lines on the cell array region and to form a gate electrode on the peripheral circuit region.