公开(公告)号：US09305928B2

公开(公告)日：2016-04-05

申请号：US14175076

申请日：2014-02-07

申请人： Samsung Electronics Co., Ltd.

发明人： Youngkuk Kim ,  Ho-Kyun An ,  Jaehyun Yeo ,  Badro Im ,  HanJin Lim ,  Sungho Jang ,  Insang Jeon

IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L21/8234

CPC分类号： H01L27/10894 ,  H01L21/823412 ,  H01L21/823462 ,  H01L27/10814 ,  H01L27/10861

摘要： Semiconductor devices having a silicon-germanium channel layer and methods of forming the semiconductor devices are provided. The methods may include forming a silicon-germanium channel layer on a substrate in a peripheral circuit region and sequentially forming a first insulating layer and a second insulating layer on the silicon-germanium channel layer. The methods may also include forming a conductive layer on the substrate, which includes a cell array region and the peripheral circuit region, and patterning the conductive layer to form a conductive line in the cell array region and a gate electrode in the peripheral circuit region. The first insulating layer may be formed at a first temperature and the second insulating layer may be formed at a second temperature higher than the first temperature.

摘要翻译： 提供具有硅 - 锗沟道层的半导体器件和形成半导体器件的方法。 所述方法可以包括在外围电路区域中的衬底上形成硅 - 锗沟道层，并且在硅 - 锗沟道层上依次形成第一绝缘层和第二绝缘层。 该方法还可以包括在衬底上形成导电层，该导电层包括电池阵列区域和外围电路区域，以及图案化导电层以在电池阵列区域中形成导线以及在外围电路区域中形成栅极电极。 第一绝缘层可以在第一温度下形成，并且第二绝缘层可以在高于第一温度的第二温度下形成。

公开(公告)号：US09812332B2

公开(公告)日：2017-11-07

申请号：US15398776

申请日：2017-01-05

申请人： Samsung Electronics Co., Ltd.

发明人： Hyun-Kwan Yu ,  Woonki Shin ,  Moonhan Park ,  DongSuk Shin ,  HanJin Lim

IPC分类号： H01L21/461 ,  H01L21/306 ,  H01L21/02 ,  H01L21/8234

CPC分类号： H01L21/30604 ,  H01L21/02057 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823481

摘要： An etching method is disclosed. The etching method comprises providing on a substrate a structure comprising a recess region formed therein. The recess region includes an inner part and a mouth part whose width is less than that of the inner part. The etching method further comprises performing a clean-then-etch process to remove at least a portion of etching object formed outside the recess region. The performing a clean-then-etch process comprises performing a cleaning process to fill at least a portion of the recess region with a cleaning solution, and performing a wet etch process to the substrate in a state that the cleaning solution remains in the recess region.

公开(公告)号：US09673272B2

公开(公告)日：2017-06-06

申请号：US14863820

申请日：2015-09-24

申请人： Samsung Electronics Co., Ltd.

发明人： Yunjung Choi ,  Se Hoon Oh ,  Jin-Su Lee ,  Younsoo Kim ,  HanJin Lim

IPC分类号： H01L29/00 ,  H01L49/02

CPC分类号： H01L28/75 ,  H01L28/90

摘要： A semiconductor device includes a lower electrode on a lower structure, a dielectric layer conformally covering a surface of the lower electrode, an upper electrode conformally covering a surface of the dielectric layer, and a barrier layer on the upper electrode. The barrier layer and the upper electrode define a space on a sidewall of the lower electrode.