公开(公告)号：US20250012556A1

公开(公告)日：2025-01-09

申请号：US18403801

申请日：2024-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younguk Jin ,  Wookrae Kim ,  Jinseob Kim ,  Jinyong Kim ,  Garam Choi ,  Daehoon Han

IPC: G01B9/02 ,  G01B9/02001 ,  G01B9/02056

Abstract: A semiconductor measurement apparatus includes lighting unit; a light receiving unit; and a control unit configured to: generate a prediction equation representing the original image, where the prediction equation is based on a plurality of elements of a Mueller matrix, approximate each of the plurality of elements of the Mueller matrix to a polynomial including bases of a Zernike polynomial and coefficients, generate optimization coefficients based on a sum of the coefficients and a difference between the prediction equation and the original image, determine whether an optimization condition is satisfied based on the optimization coefficients and a minimum value, and select a dimension based on the optimization coefficients and the bases when the optimization condition is satisfied.

公开(公告)号：US20240212725A1

公开(公告)日：2024-06-27

申请号：US18468227

申请日：2023-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Garam Choi ,  Yonghun Kim ,  Kihan Kim

IPC: G11C7/10

CPC classification number: G11C7/1048 ,  G11C2207/2254

Abstract: Provided are a memory device and a method for training per-pin operation parameters. A memory device includes a plurality of on-die termination (ODT) circuits, an impedance control (ZQ) calibration circuit configured to output a first code signal and a second code signal, and a per-pin calibration circuit. The per-pin calibration circuit may be configured to select one signal pin from among the plurality of signal pins, to compare a first input voltage level of the selected signal pin with a second input voltage level of each of the other ones of the plurality of signal pins, to generate a per-pin ODT code signal for each of the plurality of signal pins, to combine the per-pin ODT code signal with the first code signal or the second code signal, and to provide the combined per-pin ODT code signal to the respective ODT circuits.

公开(公告)号：US20220343965A1

公开(公告)日：2022-10-27

申请号：US17811503

申请日：2022-07-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HUNDAE CHOI ,  Garam Choi

IPC: G11C11/4076 ,  H03L7/081 ,  H03L7/085

Abstract: A multi-phase clock generator includes first and second variable delay lines, a first phase splitter configured to phase-split a first phase-delayed clock, output from a clock tree, to output a first divided clock and a third divided clock, a second phase splitter configured to phase-split a second phase-delayed clock, output from the clock tree, to output a second divided clock and a fourth divided clock, a first duty cycle detector configured to detect a first duty error between the first divided clock and the third divided clock, and a second duty cycle detector configured to detect a second duty error between the second divided clock and the fourth divided clock. The first variable delay line is controlled according to the first duty error, and the second variable delay line is controlled according to the second duty error.

公开(公告)号：US11437085B2

公开(公告)日：2022-09-06

申请号：US17139538

申请日：2020-12-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hundae Choi ,  Garam Choi

IPC: G11C11/4076 ,  H03L7/081 ,  H03L7/085

Abstract: A multi-phase clock generator includes first and second variable delay lines, a first phase splitter configured to phase-split a first phase-delayed clock, output from a clock tree, to output a first divided clock and a third divided clock, a second phase splitter configured to phase-split a second phase-delayed clock, output from the clock tree, to output a second divided clock and a fourth divided clock, a first duty cycle detector configured to detect a first duty error between the first divided clock and the third divided clock, and a second duty cycle detector configured to detect a second duty error between the second divided clock and the fourth divided clock. The first variable delay line is controlled according to the first duty error, and the second variable delay line is controlled according to the second duty error.

公开(公告)号：US20230400404A1

公开(公告)日：2023-12-14

申请号：US18154990

申请日：2023-01-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Garam Choi ,  Wookrae Kim ,  Jinseob Kim ,  Jinyong Kim ,  Sungho Jang ,  Daehoon Han

IPC: G01N21/21 ,  G01B11/24

CPC classification number: G01N21/21 ,  G01B11/24 ,  G01B2210/56

Abstract: A semiconductor measurement apparatus includes an illumination unit including a light source and at least one illumination polarization element, a light receiving unit including at least one light-receiving polarization element disposed on a path of light reflected by a sample, and an image sensor positioned to receive light passing through the at least one light-receiving polarization element and configured to output an original image, and a control unit configured to determine, by processing the original image, a selected critical dimension among critical dimensions of a structure included in a region of the sample. The control unit is configured to obtain a plurality of sample images by selecting regions of the original image in which a peak due to interference appears, to determine a plurality of elements included in a Mueller matrix using the plurality of sample images, and to determine the selected critical dimension based on the plurality of elements.

公开(公告)号：US11799463B2

公开(公告)日：2023-10-24

申请号：US17842881

申请日：2022-06-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hundae Choi ,  Garam Choi

IPC: H03K5/156 ,  H03L7/081 ,  G11C8/18 ,  G11C7/22 ,  G11C8/10 ,  G11C7/10

CPC classification number: H03K5/1565 ,  G11C7/222 ,  G11C8/10 ,  G11C8/18 ,  H03L7/0812 ,  G11C7/1057 ,  G11C7/1084

Abstract: A duty adjustment circuit, and a delay locked loop circuit and a semiconductor memory device including the same are provided. The duty adjustment circuit includes a pulse generator configured to generate a pulse signal at a constant pulse width regardless of a frequency of a reference clock signal, based on frequency information, a code generator configured to generate a first predetermined number of delayed pulse signals by delaying the pulse signal, as a first code in response to the pulse signal, and a duty adjuster configured to receive a delay clock signal, and generate a duty correction clock signal by adjusting a slope of rising transition and a slope of falling transition of the delay clock signal in response to the first code and a second code.

公开(公告)号：US20230194845A1

公开(公告)日：2023-06-22

申请号：US18056984

申请日：2022-11-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Garam Choi ,  Taejoong Kim ,  Jihoon Na ,  Changhoon Choi

IPC: G02B21/14 ,  G02B21/28 ,  G02B21/36 ,  G02B27/28 ,  G02B26/08 ,  G03F7/20

CPC classification number: G02B21/14 ,  G02B21/28 ,  G02B21/361 ,  G02B27/283 ,  G02B26/0816 ,  G03F7/7065

Abstract: An EUV photomask inspection apparatus includes a plurality of optical systems respectively forming different confocal points in a mask structure including an EUV photomask and a pellicle on the EUV photomask. A first optical system among the plurality of optical systems includes a first light source emitting first light having a wavelength in a visible light range, a beam splitter transmitting or reflecting the first light, an objective lens configured to allow the first light to pass through at least a portion of the mask structure to form a first focus in the mask structure, a first light detector configured to detect first reflected light reflected from the mask structure by the incident first light, and a pinhole plate in front of the first light source. The first light detector includes a detection module including a PMT and an APD, and a thermoelectric cooling.

公开(公告)号：US11568916B2

公开(公告)日：2023-01-31

申请号：US17811503

申请日：2022-07-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hundae Choi ,  Garam Choi

IPC: G11C11/4076 ,  H03L7/081 ,  H03L7/085

Abstract: A multi-phase clock generator includes first and second variable delay lines, a first phase splitter configured to phase-split a first phase-delayed clock, output from a clock tree, to output a first divided clock and a third divided clock, a second phase splitter configured to phase-split a second phase-delayed clock, output from the clock tree, to output a second divided clock and a fourth divided clock, a first duty cycle detector configured to detect a first duty error between the first divided clock and the third divided clock, and a second duty cycle detector configured to detect a second duty error between the second divided clock and the fourth divided clock. The first variable delay line is controlled according to the first duty error, and the second variable delay line is controlled according to the second duty error.

公开(公告)号：US11329654B2

公开(公告)日：2022-05-10

申请号：US17149039

申请日：2021-01-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hundae Choi ,  Garam Choi

IPC: H03L7/081 ,  G11C11/4076

Abstract: A delay circuit of a delay-locked loop (DLL) circuit includes: a phase splitter configured to split a phase of a reference clock signal to output a first reference clock signal and a second reference clock signal having a phase difference of 180 degrees; a logic gate configured to delay the second reference clock signal to output a delayed reference clock signal; and a delay line circuit including a plurality of delay cells that are cascade-connected, the delay line circuit configured to delay the first reference clock signal and the delayed reference clock signal based on a control code set, and to output a first delayed clock signal and a second delayed clock signal having a delay amount corresponding to a delay of one logic gate included in the plurality of delay cells.

公开(公告)号：US11309002B2

公开(公告)日：2022-04-19

申请号：US17109567

申请日：2020-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hundae Choi ,  Garam Choi

IPC: G11C7/22 ,  H03L7/081 ,  H03L7/085 ,  G11C8/10 ,  G11C7/10

Abstract: A delay locked loop circuit and a semiconductor memory device are provided. The delay locked loop circuit includes a phase detection and delay control circuit configured to detect a phase difference between a first internally generated clock signal the feedback clock signal to generate a first phase difference detection signal in response to a first selection signal being activated, to detect a phase difference between a second internally generated clock signal and the feedback clock signal to generate a second phase difference detection signal in response to a second selection signal being activated, and to change a code value in response to the first phase difference detection signal or the second phase difference detection signal.