公开(公告)号：US20180315850A1

公开(公告)日：2018-11-01

申请号：US16026663

申请日：2018-07-03

Applicant: STMicroelectronics, Inc.

Inventor： Qing LIU ,  John H. ZHANG

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L29/165 ,  H01L29/739 ,  H01L29/267 ,  H01L21/8238 ,  H01L29/16 ,  H01L21/8234 ,  H01L29/51 ,  H01L29/49

Abstract: A tunneling transistor is implemented in silicon, using a FinFET device architecture. The tunneling FinFET has a non-planar, vertical, structure that extends out from the surface of a doped drain formed in a silicon substrate. The vertical structure includes a lightly doped fin defined by a subtractive etch process, and a heavily-doped source formed on top of the fin by epitaxial growth. The drain and channel have similar polarity, which is opposite that of the source. A gate abuts the channel region, capacitively controlling current flow through the channel from opposite sides. Source, drain, and gate terminals are all electrically accessible via front side contacts formed after completion of the device. Fabrication of the tunneling FinFET is compatible with conventional CMOS manufacturing processes, including replacement metal gate and self-aligned contact processes. Low-power operation allows the tunneling FinFET to provide a high current density compared with conventional planar devices.

公开(公告)号：US20180286869A1

公开(公告)日：2018-10-04

申请号：US15939108

申请日：2018-03-28

Applicant: STMicroelectronics, Inc.

Inventor： John H. ZHANG

IPC: H01L27/108 ,  H01L45/00 ,  H01L21/28 ,  H01L21/8238 ,  B82Y10/00 ,  H01L33/04 ,  H01L31/0392 ,  H01L29/786 ,  H01L29/78 ,  H01L29/775 ,  H01L29/739 ,  H01L29/66 ,  H01L29/423 ,  H01L29/20 ,  H01L29/16 ,  H01L29/10 ,  H01L29/06 ,  H01L27/092 ,  H01L27/08 ,  H01L29/49

CPC classification number: H01L27/10879 ,  B82Y10/00 ,  H01L21/28008 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/823885 ,  H01L21/823892 ,  H01L27/0814 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/0653 ,  H01L29/0676 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/20 ,  H01L29/42392 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/66909 ,  H01L29/66977 ,  H01L29/7391 ,  H01L29/775 ,  H01L29/7827 ,  H01L29/7855 ,  H01L29/7856 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696 ,  H01L31/0392 ,  H01L33/04 ,  H01L45/1233 ,  H01L2029/7858

Abstract: A vertical tunneling FET (TFET) provides low-power, high-speed switching performance for transistors having critical dimensions below 7 nm. The vertical TFET uses a gate-all-around (GAA) device architecture having a cylindrical structure that extends above the surface of a doped well formed in a silicon substrate. The cylindrical structure includes a lower drain region, a channel, and an upper source region, which are grown epitaxially from the doped well. The channel is made of intrinsic silicon, while the source and drain regions are doped in-situ. An annular gate surrounds the channel, capacitively controlling current flow through the channel from all sides. The source is electrically accessible via a front side contact, while the drain is accessed via a backside contact that provides low contact resistance and also serves as a heat sink. Reliability of vertical TFET integrated circuits is enhanced by coupling the vertical TFETs to electrostatic discharge (ESD) diodes.

公开(公告)号：US20160079131A1

公开(公告)日：2016-03-17

申请号：US14951050

申请日：2015-11-24

Applicant: STMicroelectronics, Inc.

Inventor： John H. ZHANG ,  Walter KLEEMEIER ,  Paul FERREIRA ,  Ronald K. SAMPSON

IPC: H01L21/66 ,  H01L25/00

CPC classification number: H01L23/544 ,  H01L22/14 ,  H01L22/22 ,  H01L22/34 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/5446 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2924/1461 ,  H01L2924/00

Abstract: A device is provided that includes a first die having a first alignment structure that includes a plurality of first transmission columns arranged in a pattern and a second die positioned on the first die, the second die having a second alignment structure that includes a plurality of second transmission columns arranged in the same pattern as the first transmission columns. The first and second transmission columns are each coplanar with a first surface and a second surface of the first and second die, respectively.

Abstract translation: 提供了一种装置，其包括具有第一对准结构的第一管芯，所述第一对准结构包括以图案排列的多个第一传输柱和位于所述第一管芯上的第二管芯，所述第二管芯具有第二对准结构，所述第二对准结构包括多个第二 传输列以与第一传输列相同的图案排列。 第一和第二透射柱分别与第一和第二模具的第一表面和第二表面共面。

公开(公告)号：US20140293687A1

公开(公告)日：2014-10-02

申请号：US13852050

申请日：2013-03-28

Applicant: STMICROELECTRONICS, INC.

Inventor： John H. ZHANG

IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24

CPC classification number: H01L45/16 ,  B82Y10/00 ,  G11C13/0004 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/025 ,  G11C2213/76 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1683

Abstract: A semiconductor device may include a substrate, and an array of PCM memory cells above the substrate. Each PCM memory cell may include first and second vertically aligned electrodes, a first dielectric layer between the first and second electrodes, a carbon nanotube extending vertically through the first dielectric layer from the second electrode and toward the first electrode, and a PCM body between the first electrode and the at least one carbon nanotube.

Abstract translation: 半导体器件可以包括衬底，以及衬底上方的PCM存储器单元的阵列。 每个PCM存储单元可以包括第一和第二垂直排列的电极，第一和第二电极之间的第一介电层，从第二电极垂直延伸穿过第一介电层并朝向第一电极的碳纳米管， 第一电极和至少一个碳纳米管。

公开(公告)号：US20250151395A1

公开(公告)日：2025-05-08

申请号：US18983040

申请日：2024-12-16

Applicant: STMicroelectronics, Inc.

Inventor： John H. ZHANG

IPC: H10D86/00 ,  H01L21/266 ,  H01L23/528 ,  H10B10/00 ,  H10B20/00 ,  H10D30/01 ,  H10D30/60 ,  H10D30/63 ,  H10D30/69 ,  H10D62/10 ,  H10D62/832 ,  H10D84/01 ,  H10D84/03 ,  H10D84/85 ,  H10D86/01

Abstract: Single gate and dual gate FinFET devices suitable for use in an SRAM memory array have respective fins, source regions, and drain regions that are formed from portions of a single, contiguous layer on the semiconductor substrate, so that STI is unnecessary. Pairs of FinFETs can be configured as dependent-gate devices wherein adjacent channels are controlled by a common gate, or as independent-gate devices wherein one channel is controlled by two gates. Metal interconnects coupling a plurality of the FinFET devices are made of a same material as the gate electrodes. Such structural and material commonalities help to reduce costs of manufacturing high-density memory arrays.

公开(公告)号：US20180331203A1

公开(公告)日：2018-11-15

申请号：US16025982

申请日：2018-07-02

Applicant: STMICROELECTRONICS, INC.

Inventor： John H. ZHANG

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/8238

CPC classification number: H01L29/66492 ,  H01L21/26513 ,  H01L21/823814 ,  H01L21/823842 ,  H01L22/12 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/413 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/4975 ,  H01L29/66431 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7781 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Incorporation of metallic quantum dots (e.g., silver bromide (AgBr) films) into the source and drain regions of a MOSFET can assist in controlling the transistor performance by tuning the threshold voltage. If the silver bromide film is rich in bromine atoms, anion quantum dots are deposited, and the AgBr energy gap is altered so as to increase Vt. If the silver bromide film is rich in silver atoms, cation quantum dots are deposited, and the AgBr energy gap is altered so as to decrease Vt. Atomic layer deposition (ALD) of neutral quantum dots of different sizes also varies Vt. Use of a mass spectrometer during film deposition can assist in varying the composition of the quantum dot film. The metallic quantum dots can be incorporated into ion-doped source and drain regions. Alternatively, the metallic quantum dots can be incorporated into epitaxially doped source and drain regions.

公开(公告)号：US20170229391A1

公开(公告)日：2017-08-10

申请号：US15499665

申请日：2017-04-27

Applicant: STMICROELECTRONICS, INC.

Inventor： John H. ZHANG

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/528 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5228 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L27/0676 ,  H01L27/0682 ,  H01L27/0802 ,  H01L28/20 ,  H01L28/24 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for making a semiconductor device may include forming a first dielectric layer above a semiconductor substrate, forming a first trench in the first dielectric layer, filling the first trench with electrically conductive material, removing upper portions of the electrically conductive material to define a lower conductive member with a recess thereabove, forming a filler dielectric material in the recess to define a second trench. The method may further include filling the second trench with electrically conductive material to define an upper conductive member, forming a second dielectric layer over the first dielectric layer and upper conductive member, forming a first via through the second dielectric layer and underlying filler dielectric material to the lower conductive member, and forming a second via through the second dielectric layer to the upper conductive member.

公开(公告)号：US20170092778A1

公开(公告)日：2017-03-30

申请号：US15280879

申请日：2016-09-29

Applicant: STMICROELECTRONICS, INC.

Inventor： John H. ZHANG

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/78642 ,  H01J21/105 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/78696

Abstract: A vacuum channel transistor having a vertical gate-all-around (GAA) architecture provides high performance for high-frequency applications, and features a small footprint compared with existing planar devices. The GAA vacuum channel transistor features stacked, tapered source and drain regions that are formed by notching a doped silicon pillar using a lateral oxidation process. A temporary support structure is provided for the pillar during formation of the vacuum channel. Performance of the GAA vacuum channel transistor can be tuned by replacing air in the channel with other gases such as helium, neon, or argon. A threshold voltage of the GAA vacuum channel transistor can be adjusted by altering dopant concentrations of the silicon pillar from which the source and drain regions are formed.

公开(公告)号：US20160380118A1

公开(公告)日：2016-12-29

申请号：US15260206

申请日：2016-09-08

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing LIU ,  John H. ZHANG

IPC: H01L29/84 ,  H01L21/306 ,  H01L21/02 ,  H01H49/00 ,  H01H59/00

CPC classification number: H01L29/84 ,  B82B3/00 ,  H01H1/0094 ,  H01H49/00 ,  H01H50/005 ,  H01H59/0009 ,  H01H2001/0084 ,  H01L21/02532 ,  H01L21/30608

Abstract: An integrated transistor in the form of a nanoscale electromechanical switch eliminates CMOS current leakage and increases switching speed. The nanoscale electromechanical switch features a semiconducting cantilever that extends from a portion of the substrate into a cavity. The cantilever flexes in response to a voltage applied to the transistor gate thus forming a conducting channel underneath the gate. When the device is off, the cantilever returns to its resting position. Such motion of the cantilever breaks the circuit, restoring a void underneath the gate that blocks current flow, thus solving the problem of leakage. Fabrication of the nano-electromechanical switch is compatible with existing CMOS transistor fabrication processes. By doping the cantilever and using a back bias and a metallic cantilever tip, sensitivity of the switch can be further improved. A footprint of the nano-electromechanical switch can be as small as 0.1×0.1 μm2.

Abstract translation: 纳米级机电开关形式的集成晶体管消除了CMOS电流泄漏并提高了开关速度。 纳米尺度的机电开关具有从衬底的一部分延伸到空腔中的半导体悬臂。 悬臂响应于施加到晶体管栅极的电压而弯曲，从而在栅极下形成导电沟道。 当设备关闭时，悬臂返回到其静止位置。 悬臂的这种运动打破了电路，恢复了阻挡电流的门下方的空隙，从而解决了泄漏问题。 纳米机电开关的制造与现有的CMOS晶体管制造工艺兼容。 通过掺杂悬臂并使用背偏压和金属悬臂尖，可以进一步提高开关的灵敏度。 纳米机电开关的占地面积可以小至0.1×0.1μm2。

公开(公告)号：US20130093289A1

公开(公告)日：2013-04-18

申请号：US13645658

申请日：2012-10-05

Applicant: STMicroelectronics, Inc.

Inventor： John H. ZHANG

IPC: H01L41/09 ,  H01L41/22

CPC classification number: H01L41/332 ,  H01L41/0973

Abstract: A support structure includes an internal cavity. An elastic membrane extends to divide the internal cavity into a first chamber and a second chamber. The elastic membrane includes a nanometric-sized pin hole extending there through to interconnect the first chamber to the second chamber. The elastic membrane is formed of a first electrode film and a second electrode film separated by a piezo insulating film. Electrical connection leads are provided to support application of a bias current to the first and second electrode films of the elastic membrane. In response to an applied bias current, the elastic membrane deforms by bending in a direction towards one of the first and second chambers so as to produce an increase in a diameter of the pin hole.

Abstract translation: 支撑结构包括内腔。 弹性膜延伸以将内腔分成第一腔室和第二腔室。 弹性膜包括在其上延伸的纳米尺寸的针孔，以将第一腔室与第二腔室相互连接。 弹性膜由第一电极膜和由压电绝缘膜隔开的第二电极膜形成。 提供电连接引线以支持向弹性膜的第一和第二电极膜施加偏置电流。 响应于所施加的偏置电流，弹性膜通过沿朝向第一和第二腔室之一的方向弯曲而变形，从而产生销孔直径的增加。