公开(公告)号：US09508589B2

公开(公告)日：2016-11-29

申请号：US14283162

申请日：2014-05-20

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Kern Rim ,  Zhongze Wang ,  Jeffrey Junhao Xu ,  Xiangdong Chen ,  Choh Fei Yeap

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76802 ,  H01L21/76814 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/48 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of fabricating middle of line (MOL) layers and devices including MOL layers. A method in accordance with an aspect of the present disclosure includes depositing a hard mask across active contacts to terminals of semiconductor devices of a semiconductor substrate. Such a method also includes patterning the hard mask to selectively expose some of the active contacts and selectively insulate some of the active contacts. The method also includes depositing a conductive material on the patterned hard mask and the exposed active contacts to couple the exposed active contacts to each other over an active area of the semiconductor devices.

Abstract translation: 制造中间线（MOL）层和包括MOL层的器件的方法。 根据本公开的一个方面的方法包括将半导体衬底的半导体器件的端子上的活性触点沉积硬掩模。 这种方法还包括图案化硬掩模以选择性地暴露一些有源触点并选择性地绝缘一些有源触点。 该方法还包括在图案化的硬掩模和暴露的有源触点上沉积导电材料，以将暴露的有源触点彼此连接在半导体器件的有效区域上。

公开(公告)号：US09478490B2

公开(公告)日：2016-10-25

申请号：US14483110

申请日：2014-09-10

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong Zhu ,  Stanley Seungchul Song ,  Kern Rim ,  Zhongze Wang ,  Jeffrey Junhao Xu

IPC: H01L21/02 ,  H01L27/108 ,  H01L21/00 ,  H01L23/522 ,  H01L49/02 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/08

CPC classification number: H01L23/5223 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/823475 ,  H01L27/0805 ,  H01L28/60 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A device capacitor structure within middle of line (MOL) layers includes a first MOL interconnect layer. The first MOL interconnect layer may include active contacts between a set of dummy gate contacts on an active surface of a semiconductor substrate. The device capacitor structure also includes a second MOL interconnect layer. The second MOL interconnect layer may include a set of stacked contacts directly on exposed ones of the active contacts. The second MOL interconnect layer may also include a set of fly-over contacts on portions of an etch-stop layer on some of the active contacts. The fly-over contacts and the stacked contacts may provide terminals of a set of device capacitors.

Abstract translation: 线路（MOL）层中间的器件电容器结构包括第一MOL互连层。 第一MOL互连层可以包括半导体衬底的有源表面上的一组虚拟栅极触点之间的有源触点。 器件电容器结构还包括第二MOL互连层。 第二MOL互连层可以直接在活动触点的暴露的一个上包括一组堆叠的触点。 第二MOL互连层还可以包括在一些有源触点上的蚀刻停止层的部分上的一组飞越触点。 飞越触点和堆叠的触点可以提供一组器件电容器的端子。

公开(公告)号：US20160240539A1

公开(公告)日：2016-08-18

申请号：US14620480

申请日：2015-02-12

Applicant: QUALCOMM Incorporated

Inventor： Niladri Narayan Mojumder ,  Ritu Chaba ,  Ping Liu ,  Stanley Seungchul Song ,  Zhongze Wang ,  Choh Fei Yeap

IPC: H01L27/11 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L27/1104 ,  G11C8/14 ,  G11C8/16 ,  G11C11/418 ,  G11C11/419 ,  H01L21/3213 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/11

Abstract: An apparatus includes a first metal layer coupled to a bit cell. The apparatus also includes a third metal layer including a write word line that is coupled to the bit cell. The apparatus further includes a second metal layer between the first metal layer and the third metal layer. The second metal layer includes two read word lines coupled to the bit cell.

Abstract translation: 一种装置包括耦合到位单元的第一金属层。 该装置还包括第三金属层，其包括耦合到位单元的写入字线。 该装置还包括在第一金属层和第三金属层之间的第二金属层。 第二金属层包括耦合到位单元的两个读字线。

公开(公告)号：US09413349B1

公开(公告)日：2016-08-09

申请号：US14676228

申请日：2015-04-01

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Xiao Lu ,  Xiaonan Chen ,  Zhongze Wang ,  Choh Fei Yeap

IPC: G11C16/10 ,  H03K17/687 ,  H01L29/792 ,  H01L29/51 ,  H01L27/115 ,  G11C16/04

CPC classification number: H03K17/687 ,  G11C16/0466 ,  G11C16/10 ,  H01L27/1052 ,  H01L27/11563 ,  H01L27/11568 ,  H01L29/51 ,  H01L29/792

Abstract: Aspects disclosed in the detailed description include high-k (HK)/metal gate (MG) (HK/MG) multi-time programmable (MTP) switching devices, and related systems and methods. One type of HK/MG MTP switching device is an MTP metal-oxide semiconductor (MOS) field-effect transistor (MOSFET). When the MTP MOSFET is programmed, a charge trap may build up in the MTP MOSFET due to a switching electrical current induced by a switching voltage. The charge trap reduces the switching window and endurance of the MTP MOSFET, thus reducing reliability in accessing the information stored in the MTP MOSFET. In this regard, an HK/MG MTP switching device comprising the MTP MOSFET is configured to eliminate the switching electrical current when the MTP MOSFET is programmed. By eliminating the switching electrical current, it is possible to avoid a charge trap in the MTP MOSFET, thus restoring the switching window and endurance of the MTP MOSFET for reliable information access.

Abstract translation: 在详细描述中公开的方面包括高k（HK）/金属门（MG）（HK / MG）多时间可编程（MTP）交换设备以及相关的系统和方法。 一种类型的HK / MG MTP开关器件是MTP金属氧化物半导体（MOS）场效应晶体管（MOSFET）。 当编程MTP MOSFET时，由于开关电压引起的开关电流，电荷陷阱可能会积累在MTP MOSFET中。 电荷阱减少了MTP MOSFET的开关窗口和耐久性，从而降低了访问存储在MTP MOSFET中的信息的可靠性。 在这方面，包括MTP MOSFET的HK / MG MTP开关器件被配置为在编程MTP MOSFET时消除开关电流。 通过消除开关电流，可以避免MTP MOSFET中的电荷陷阱，从而恢复MTP MOSFET的开关窗口和耐用性，从而实现可靠的信息访问。

公开(公告)号：US09378803B2

公开(公告)日：2016-06-28

申请号：US13842263

申请日：2013-03-15

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Zhongze Wang

IPC: G06F17/50 ,  G11C11/4074 ,  G11C5/14 ,  G11C7/04 ,  G11C11/413 ,  G11C11/417

CPC classification number: G11C11/4074 ,  G06F17/5072 ,  G11C5/147 ,  G11C7/04 ,  G11C11/413 ,  G11C11/417

Abstract: A method includes measuring a temperature of a sensor associated with a memory array. The method also includes calculating, at a voltage regulating device, an operating voltage based on the temperature and based on fabrication data associated with the memory array. The method further includes regulating, at the voltage regulating device, a voltage provided to the memory array based on the operating voltage.

Abstract translation: 一种方法包括测量与存储器阵列相关联的传感器的温度。 该方法还包括在电压调节装置处基于温度和基于与存储器阵列相关联的制造数据来计算工作电压。 该方法还包括在电压调节装置处基于工作电压调节提供给存储器阵列的电压。

公开(公告)号：US09373387B1

公开(公告)日：2016-06-21

申请号：US14659937

申请日：2015-03-17

Applicant: QUALCOMM Incorporated

Inventor： Niladri Narayan Mojumder ,  Ping Liu ,  Stanley Seungchul Song ,  Zhongze Wang ,  Choh Fei Yeap

IPC: G11C11/00 ,  G11C11/417 ,  G06F17/50 ,  G11C11/412

Abstract: Aspects disclosed include static random access memory (SRAM) arrays having substantially constant operational yields across multiple modes of operation. In one aspect, a method of designing SRAM arrays with multiple modes operation is provided. The method includes determining performance characteristics associated with each mode of operation. SRAM bit cells configured to operate in each mode of operation are provided to the SRAM array. SRAM bit cells are biased to operate in a mode of operation using dynamic adaptive assist techniques, wherein the SRAM bit cells achieve a substantially constant operational yield across the modes. The SRAM bit cells have a corresponding type, wherein the number of SRAM bit cell types in the method is less than the number of modes of operation. Thus, each SRAM array may achieve a particular mode of operation without requiring a separate SRAM bit cell type for each mode, thereby reducing costs.

公开(公告)号：US20140312500A1

公开(公告)日：2014-10-23

申请号：US13864344

申请日：2013-04-17

Applicant: QUALCOMM INCORPORATED

Inventor： John J. Zhu ,  Zhongze Wang ,  Yang Da

IPC: H01L21/283 ,  H01L21/768 ,  H01L23/50

CPC classification number: H01L21/76894 ,  G03F7/7045 ,  G03F7/70466 ,  H01L21/28123 ,  H01L21/283 ,  H01L21/31 ,  H01L21/469 ,  H01L21/76892 ,  H01L21/76895 ,  H01L23/50 ,  H01L24/27 ,  H01L24/31 ,  H01L2924/0002 ,  H01L2924/12042 ,  H01L2924/00

Abstract: Features are fabricated on a semiconductor chip. The features are smaller than the threshold of the lithography used to create the chip. A method includes patterning a first portion of a feature (such as a local interconnect) and a second portion of the feature to be separated by a predetermined distance, such as a line tip to tip space or a line space. The method further includes patterning the first portion with a cut mask to form a first sub-portion (e.g., a contact) and a second sub-portion. A dimension of the first sub-portion is less than a dimension of a second predetermined distance, which may be a line length resolution of a lithographic process having a specified width resolution. A feature of a semiconductor device includes a first portion and a second portion having a dimension less than a lithographic resolution of the first portion.

Abstract translation: 特征是在半导体芯片上制造的。 这些特征小于用于制造芯片的光刻的阈值。 一种方法包括图案化特征（例如局部互连）的第一部分和要被分离预定距离的特征的第二部分，例如线尖到尖端空间或线空间。 该方法还包括用切割掩模图案化第一部分以形成第一子部分（例如，接触）和第二子部分。 第一子部分的尺寸小于第二预定距离的尺寸，其可以是具有指定宽度分辨率的光刻工艺的线长分辨率。 半导体器件的特征包括第一部分和具有小于第一部分的光刻分辨率的尺寸的第二部分。

公开(公告)号：US08799847B1

公开(公告)日：2014-08-05

申请号：US13838462

申请日：2013-03-15

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Zhongze Wang ,  Choh fei Yeap

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5068 ,  H01L29/66795

Abstract: Methods for designing fin-based field effect transistors (FinFETs) are disclosed. In one embodiment, an initial FinFET design is evaluated to ascertain the space between fins (i.e., the “fin pitch”). Additionally, the spacing between interconnect metal modules (i.e., the “metal pitch”) is ascertained. A ratio of metal pitch to fin pitch is established. From this initial ratio, isotropically scaled sizes are considered along with anisotropically scaled sizes. The variously scaled sizes are compared to design criteria to see what new size best fits the design criteria.

Abstract translation: 公开了用于设计基于鳍的场效应晶体管（FinFET）的方法。 在一个实施例中，评估初始FinFET设计以确定翅片之间的空间（即，“翅片间距”）。 此外，确定互连金属模块之间的间隔（即，“金属间距”）。 确定了金属间距与翅片间距的比率。 从这个初始比例来看，各向异性缩放的尺寸以及各向异性尺寸的尺寸被考虑。 将不同尺寸的尺寸与设计标准进行比较，以了解最符合设计标准的新尺寸。

公开(公告)号：US20140210043A1

公开(公告)日：2014-07-31

申请号：US14227415

申请日：2014-03-27

Applicant: QUALCOMM Incorporated

Inventor： Zhongze Wang ,  John Jianhong Zhu ,  Xia Li

IPC: H01L23/525 ,  H01L21/768

CPC classification number: H01L23/5252 ,  G11C17/16 ,  H01L23/5228 ,  H01L27/11206 ,  H01L27/11286 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One feature pertains to an integrated circuit that includes an antifuse having a conductor-insulator-conductor structure. The antifuse includes a first conductor plate, a dielectric layer, and a second conductor plate, where the dielectric layer is interposed between the first and second conductor plates. The antifuse transitions from an open circuit state to a closed circuit state if a programming voltage VPP greater than or equal to a dielectric breakdown voltage VBD of the antifuse is applied to the first conductor plate and the second conductor plate. The first conductor plate has a total edge length that is greater than two times the sum of its maximum width and maximum length dimensions. The first conductor plate's top surface area may also be less than the product of its maximum length and maximum width.

Abstract translation: 一个特征涉及包括具有导体 - 绝缘体 - 导体结构的反熔丝的集成电路。 反熔丝包括第一导体板，电介质层和第二导体板，其中电介质层插在第一和第二导体板之间。 如果大于等于反熔丝的绝缘击穿电压VBD的编程电压VPP被施加到第一导体板和第二导体板，则反熔丝从开路状态转变到闭合状态。 第一导体板的总边缘长度大于其最大宽度和最大长度尺寸之和的两倍。 第一导体板的顶表面积也可以小于其最大长度和最大宽度的乘积。

公开(公告)号：US20140131799A1

公开(公告)日：2014-05-15

申请号：US14156785

申请日：2014-01-16

Applicant: QUALCOMM Incorporated

Inventor： Zhongze Wang ,  Choh fei Yeap ,  Ping Liu

IPC: H01L27/088 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L21/823412 ,  H01L21/823462 ,  H01L21/823807 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/66492 ,  H01L29/7833 ,  Y02D70/00

Abstract: An apparatus for selectively improving integrated circuit performance is provided. In an example, an integrated circuit is fabricated according to an integrated circuit layout. A critical portion of the integrated circuit layout determines a speed of the integrated circuit, where at least a part of the critical portion includes at least one of a halo implant region, lightly doped drain (LDD) implant region, and source drain extension (SDE) implant region. A marker layer comprises the part of the critical portion that includes the at least one of the halo implant region, the lightly doped drain (LDD) implant region, and the source drain extension (SDE) implant region, and includes at least one transistor formed therefrom.

Abstract translation: 提供了一种用于选择性地提高集成电路性能的装置。 在一个示例中，根据集成电路布局制造集成电路。 集成电路布局的关键部分确定集成电路的速度，其中临界部分的至少一部分包括光晕注入区域，轻掺杂漏极（LDD）注入区域和源极漏极延伸（SDE）中的至少一个 ）植入区域。 标记层包括关键部分的包括所述卤素注入区，轻掺杂漏极（LDD）注入区和源极漏极延伸（SDE）注入区）中的至少一个的部分，并且包括形成的至少一个晶体管 由此。