公开(公告)号：US20240120847A1

公开(公告)日：2024-04-11

申请号：US17961264

申请日：2022-10-06

Applicant: Google LLC

Inventor： Shuai Jiang ,  Xin Li ,  Woon-Seong Kwon ,  Cheng Chung Yang ,  Qiong Wang ,  Nam Hoon Kim ,  Mikhail Popovich ,  Houle Gan ,  Chenhao Nan

IPC: H02M3/335 ,  H02M1/00

CPC classification number: H02M3/33576 ,  H02M1/0067 ,  H02M3/33571

Abstract: A voltage regulator having a multiple of main stages and at least one accelerated voltage regulator (AVR) bridge is provided. The main stages may respond to low frequency current transients and provide DC output voltage regulation. The AVR bridges are switched much faster than the main stages and respond to high frequency current transients without regulating the DC output voltage. The AVR bridge frequency response range can overlap with the main stage frequency response range, and the lowest frequency to which the AVR bridges respond may be set lower than the highest frequency to which the main stages respond.

公开(公告)号：US20230420494A1

公开(公告)日：2023-12-28

申请号：US18244716

申请日：2023-09-11

Applicant: Google LLC

Inventor： Nam Hoon Kim ,  Teckgyu Kang ,  Scott Lee Kirkman ,  Woon-Seong Kwon

IPC: H10N69/00 ,  H01L21/48 ,  H01L23/13 ,  H01L23/498 ,  H01L23/00 ,  H01L25/16

CPC classification number: H01L28/90 ,  H01L21/486 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/81 ,  H01L25/16 ,  H01L2224/16225 ,  H01L2924/1433 ,  H01L2924/19041 ,  H01L2924/19102

Abstract: This disclosure relates to deep trench capacitors embedded in a package substrate on which an integrated circuit is mounted. In some aspects, a chip package includes an integrated circuit die that has a power distribution circuit for one or more circuits of the integrated circuit. The chip package also includes a substrate different from the integrated circuit and having a first surface on which the integrated circuit die is mounted and a second surface opposite the first surface. The substrate includes one or more cavities formed in at least one of the first surface or the second surface. The chip package also includes one or more deep trench capacitors disposed in at least one of the one or more cavities. Each deep trench capacitor is connected to the power distribution circuit by conductors.

公开(公告)号：US10548240B1

公开(公告)日：2020-01-28

申请号：US16246013

申请日：2019-01-11

Applicant: Google LLC

Inventor： Madhusudan Krishnan Iyengar ,  Christopher Gregory Malone ,  Yuan Li ,  Jorge Padilla ,  Woon-Seong Kwon ,  Teckgyu Kang ,  Norman Paul Jouppi

IPC: H05K7/20 ,  F28F3/02 ,  H01L23/473

Abstract: A server tray package includes a motherboard assembly that includes a plurality of data center electronic devices; and a liquid cold plate assembly. The liquid cold plate assembly includes a base portion mounted to the motherboard assembly, the base portion and motherboard assembly defining a volume that at least partially encloses the plurality of data center electronic devices; and a top portion mounted to the base portion and including a heat transfer member that includes a first number of inlet ports and a second number of outlet ports that are in fluid communication with a cooling liquid flow path defined through the heat transfer member, the first number of inlet ports being different that the second number of outlet ports.

公开(公告)号：US10548239B1

公开(公告)日：2020-01-28

申请号：US16167905

申请日：2018-10-23

Applicant: Google LLC

Inventor： Madhusudan Krishnan Iyengar ,  Gregory Sizikov ,  Yuan Li ,  Jorge Padilla ,  Woon-Seong Kwon ,  Teckgyu Kang

IPC: H05K7/20 ,  H05K7/14

Abstract: A cooling system, for example, for rack mounted electronic devices (e.g., servers, processors, memory, networking devices or otherwise) in a data center. In various disclosed implementations, the cooling system may be or include a liquid cold plate assembly that is part of or integrated with a server tray package. In some implementations, the liquid cold plate assembly includes a base portion and a top portion that, in combination, form a cooling liquid flow path through which a cooling liquid is circulated and a thermal interface between one or more heat generating devices and the cooling liquid.

公开(公告)号：US20240347414A1

公开(公告)日：2024-10-17

申请号：US18634198

申请日：2024-04-12

Applicant: Google LLC

Inventor： Madhusudan K. Iyengar ,  Christopher Malone ,  Woon-Seong Kwon ,  Emad Samadiani ,  Melanie Beauchemin ,  Padam Jain ,  Teckgyu Kang ,  Yuan Li ,  Connor Burgess ,  Norman Paul Jouppi ,  Nicholas Stevens-Yu ,  Yingying Wang

IPC: H01L23/373 ,  H01L23/00 ,  H01L25/065 ,  H05K3/34 ,  H05K7/20

CPC classification number: H01L23/3732 ,  H01L23/562 ,  H01L24/32 ,  H01L24/83 ,  H05K3/3436 ,  H05K7/20254 ,  H01L25/0655 ,  H01L2223/58 ,  H01L2224/32 ,  H01L2224/32245 ,  H01L2924/15311 ,  H05K2201/10378 ,  H05K2203/041

Abstract: A method of manufacturing a chip assembly comprises joining an in-process unit to a printed circuit board; reflowing a bonding material disposed between and electrically connecting the in-process unit with the printed circuit board, the bonding material having a first reflow temperature; and then joining a heat distribution device to the plurality of semiconductor chips using a thermal interface material (“TIM”) having a second reflow temperature that is lower than the first reflow temperature. The in-process unit further comprises a substrate having an active surface, a passive surface, and contacts exposed at the active surface; an interposer electrically connected to the substrate; a plurality of semiconductor chips overlying the substrate and electrically connected to the substrate through the interposer, and a stiffener overlying the substrate and having an aperture extending therethrough, the plurality of semiconductor chips being positioned within the aperture.

公开(公告)号：US11978721B2

公开(公告)日：2024-05-07

申请号：US17579012

申请日：2022-01-19

Applicant: Google LLC

Inventor： Woon-Seong Kwon ,  Namhoon Kim ,  Teckgyu Kang ,  Ryohei Urata

IPC: H01L25/065 ,  G02B6/42 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L23/538 ,  H01L25/16 ,  H01L25/04 ,  H01L25/075 ,  H01L31/12 ,  H10K39/00

CPC classification number: H01L25/0652 ,  G02B6/4257 ,  H01L23/3121 ,  H01L23/3672 ,  H01L23/49805 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/5385 ,  H01L23/5386 ,  H01L25/162 ,  H01L25/041 ,  H01L25/075 ,  H01L25/167 ,  H01L31/12 ,  H01L2225/06517 ,  H10K39/601

Abstract: The technology relates to an integrated circuit (IC) package. The IC package may include a substrate. An IC die may be mounted to the substrate. One or more photonic modules may be attached to the substrate and one or more serializer/deserializer (SerDes) interfaces may connect the IC die to the one or more photonic modules. The IC die may be an application specific integrated circuit (ASIC) die and the one or more photonic modules may include a photonic integrated circuit (PIC) and fiber array. The one or more photonic modules may be mounted to one or more additional substrates which may be attached to the substrate via one or more sockets.

公开(公告)号：US11967538B2

公开(公告)日：2024-04-23

申请号：US17226177

申请日：2021-04-09

Applicant: Google LLC

Inventor： Woon-Seong Kwon ,  Xiaojin Wei ,  Madhusudan K. Iyengar ,  Teckgyu Kang

IPC: H01L23/367 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/18

CPC classification number: H01L23/3675 ,  H01L21/4882 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/18 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/1433 ,  H01L2924/1434

Abstract: An IC die includes a temperature control element suitable for three-dimensional IC package with enhanced thermal control and management. The temperature control element may be formed as an integral part of an IC die that may assist temperature control of the IC die when in operation. The temperature control element may include a heat dissipation material disposed therein to assist dissipating thermal energy generated by the plurality of devices in the IC die during operation.

公开(公告)号：US20230402430A1

公开(公告)日：2023-12-14

申请号：US18239368

申请日：2023-08-29

Applicant: Google LLC

Inventor： Namhoon Kim ,  Woon-Seong Kwon ,  Houle Gan ,  Yujeong Shim ,  Mikhail Popovich ,  Teckgyu Kang

IPC: H01L25/065

CPC classification number: H01L25/0657 ,  H01L28/10 ,  H01L28/40 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06548

Abstract: The technology relates to an integrated circuit (IC) package. The IC package may include a packaging substrate, an IC die, and an integrated voltage regulator die. The IC die may include a metal layer and a silicon layer. The metal layer may be connected to the packaging substrate. The integrated voltage regulator die may be positioned adjacent to the silicon layer and connected to the packaging substrate via one or more through mold vias or through dielectric vias. The IC die may be an application specific integrated circuit (ASIC) die.

公开(公告)号：US11830855B2

公开(公告)日：2023-11-28

申请号：US17667104

申请日：2022-02-08

Applicant: Google LLC

Inventor： Namhoon Kim ,  Woon-Seong Kwon ,  Houle Gan ,  Yujeong Shim ,  Mikhail Popovich ,  Teckgyu Kang

IPC: H01L25/065 ,  H01L49/02

CPC classification number: H01L25/0657 ,  H01L28/10 ,  H01L28/40 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06548

Abstract: The technology relates to an integrated circuit (IC) package. The IC package may include a packaging substrate, an IC die, and an integrated voltage regulator die. The IC die may include a metal layer and a silicon layer. The metal layer may be connected to the packaging substrate. The integrated voltage regulator die may be positioned adjacent to the silicon layer and connected to the packaging substrate via one or more through mold vias or through dielectric vias. The IC die may be an application specific integrated circuit (ASIC) die.

公开(公告)号：US20230335928A1

公开(公告)日：2023-10-19

申请号：US17722860

申请日：2022-04-18

Applicant: Google LLC

Inventor： William F. Edwards, JR. ,  Xu Zuo ,  Ryohei Urata ,  Melanie Beauchemin ,  Woon-Seong Kwon ,  Shinnosuke Yamamoto ,  Houle Gan ,  Yujeong Shim

IPC: H01R12/70 ,  H01R13/66 ,  H01R13/533

CPC classification number: H01R12/7064 ,  H01R13/533 ,  H01R13/6683

Abstract: An assembly includes a printed circuit board (“PCB”). An aperture extends through the PCB. The assembly also includes an array of pins and a processor package. The array of pins extends around a perimeter of the aperture, and the processor package extends over the aperture. The processor package is pressed against the array of pins by a compressive force couple.