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公开(公告)号：US20190103483A1
公开(公告)日：2019-04-04
申请号：US16137235
申请日：2018-09-20
Inventor： Hokyun AHN , Min Jeong SHIN , Jeong Jin KIM , Hae Cheon KIM , Jae Won DO , Byoung-Gue MIN , Hyung Sup YOON , Hyung Seok LEE , Jong-Won LIM , Sungjae CHANG , Hyunwook JUNG , Kyu Jun CHO , Dong Min KANG , Dong-Young KIM , SEONG-IL KIM , Sang-Heung LEE , Jongmin LEE , Hong Gu JI
IPC: H01L29/78 , H01L29/20 , H01L29/45 , H01L29/417 , H01L29/423 , H01L29/66 , H01L21/3065
Abstract: Provided is a semiconductor device including a substrate in which an insulation layer is disposed between a first semiconductor layer and a second semiconductor layer, a through-hole penetrating through the substrate, the through-hole having a first hole penetrating through the first semiconductor layer and a second hole penetrating through the insulation layer and the second semiconductor layer from a bottom surface of the first hole, an epi-layer disposed inside the through-hole, a drain electrode disposed inside the second hole and contacting one surface of the epi-layer, and a source electrode and a gate electrode which are disposed on the other surface of the epi-layer.
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公开(公告)号：US20190081166A1
公开(公告)日：2019-03-14
申请号：US16028612
申请日：2018-07-06
Inventor： Jae Won DO , Dong Min KANG , Dong-Young KIM , SEONG-IL KIM , Hae Cheon KIM , Byoung-Gue MIN , Min Jeong SHIN , Hokyun AHN , Hyung Sup YOON , Sang-Heung LEE , Jongmin LEE , Jong-Won LIM , Sungjae CHANG , Yoo Jin JANG , Hyunwook JUNG , Kyu Jun CHO , Hong Gu JI
IPC: H01L29/778 , H01L29/423 , H01L29/66 , H01L29/06 , H01L29/10 , H01L29/205
Abstract: Provided is a gate-all-around device. The gate-all-around device includes a substrate, a pair of heterojunction source/drain regions provided on the substrate, a heterojunction channel region provided between the pair of heterojunction source/drain regions, and a pair of ohmic electrodes provided on the pair of heterojunction source/drain regions, respectively. Each of the pair of heterojunction source/drain regions includes a pair of two-dimensional electron gas layers. The pair of ohmic electrodes extends toward an upper surface of the substrate and pass through the pair of heterojunction source/drain regions, respectively.
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公开(公告)号：US20180145684A1
公开(公告)日：2018-05-24
申请号：US15654792
申请日：2017-07-20
Inventor： Woojin CHANG , Jong-Won LIM , Dong Min KANG , Dong-Young KIM , Seong-il KIM , Hae Cheon KIM , Jae Won DO , BYOUNG-GUE MIN , Min Jeong SHIN , Hokyun AHN , Hyung Sup YOON , Sang-Heung LEE , JONGMIN LEE , Sungjae CHANG , Yoo Jin JANG , HYUNWOOK JUNG , Kyu Jun CHO , Hong Gu JI
IPC: H03K17/687 , H03K17/693 , G11C5/14 , H03K19/0175 , H03K3/353
CPC classification number: H03K17/687 , G11C5/14 , H03K3/353 , H03K17/08122 , H03K17/102 , H03K17/122 , H03K17/145 , H03K17/162 , H03K17/28 , H03K17/693 , H03K19/0175
Abstract: Provided is a cascode circuit including first and second transistors connected between a drain terminal and a source terminal in cascode form, a level sifter configured to change a voltage level of a switching control signal applied to a gate terminal and provide the changed switching control signal to a gate of the first transistor, a buffer configured to delay the switching control signal and provide the delayed switching control signal to a gate of the second transistor, and a first resistor connected between the level shifter and the gate of the first transistor.
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Patent Agency Ranking
公开(公告)号：US20170237171A1
公开(公告)日：2017-08-17
申请号：US15229891
申请日：2016-08-05
Inventor： Dong-Young KIM , Dong Min KANG , SEONG-IL KIM , Hae Cheon KIM , Jae Won DO , Byoung-Gue MIN , Ho Kyun AHN , Hyung Sup YOON , Sang-Heung LEE , Jong Min LEE , Jong-Won LIM , Yoo Jin JANG , Hyun Wook JUNG , Kyu Jun CHO , Chull Won JU
CPC classification number: H01Q9/0407 , H01Q1/50 , H01Q9/0442
Abstract: Provided herein is a patch antenna including a multilayered substrate on which a plurality of dielectric layers are laminated; at least one metal pattern layer disposed between the plurality of dielectric layers outside a central area of the multilayered substrate; an antenna patch disposed on an upper surface of the multilayered substrate and within the central area; a ground layer disposed on a lower surface of the multilayered substrate; a plurality of connection via patterns penetrating the plurality of dielectric layers to connect the metal pattern layer and the ground layer, and surrounding the central area; a transmission line comprising a first transmission line unit disposed on the upper surface of the multilayered substrate and located outside the central area, and a second transmission line unit disposed on the upper surface of the multilayered substrate and located within the central area; and an impedance transformer located below the second transmission line unit within the central area of the multilayered substrate.
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15.发明申请SEMICONDUCTOR DEVICE HAVING STABLE GATE STRUCTURE AND METHOD OF MANUFACTURING THE SAME 有权具有稳定的门结构的半导体器件及其制造方法公开(公告)号：US20150236108A1
公开(公告)日：2015-08-20
申请号：US14328247
申请日：2014-07-10
Inventor： Seong Il KIM , Dong Min KANG , Sang Heung LEE , Ho Kyun AHN , Hyung Sup YOON , Byoung Gue MIN , Jong Won LIM
IPC: H01L29/423 , H01L21/283 , H01L29/778
CPC classification number: H01L29/42312 , H01L21/28114 , H01L21/28587 , H01L21/28593 , H01L29/42316 , H01L29/66863 , H01L29/778 , H01L29/812
Abstract: Disclosed are a semiconductor device having a stable gate structure, and a manufacturing method thereof, in which a gate structure is stabilized by additionally including a plurality of gate feet under a gate head in a width direction of the gate head so as to serve as supporters in a gate structure including a fine gate foot having a length of 0.2 μm or smaller, and the gate head having a predetermined size. Accordingly, it is possible to prevent the gate electrode of the semiconductor device from collapsing, and improve reliability of the semiconductor device during or after the process of the semiconductor device.
Abstract translation: 公开了一种具有稳定的栅极结构的半导体器件及其制造方法，其中通过在栅极头的宽度方向上的栅极头附近还包括多个栅极脚来稳定栅极结构，以作为支撑体 在包括具有0.2μm或更小的长度的精细栅极脚的栅极结构中，并且栅极头具有预定尺寸。 因此，可以防止半导体器件的栅电极塌陷，并且在半导体器件的处理期间或之后提高半导体器件的可靠性。
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公开(公告)号：US20210143182A1
公开(公告)日：2021-05-13
申请号：US17094931
申请日：2020-11-11
Inventor： Sung-Jae CHANG , Dong Min KANG , Sung-Bum BAE , Hyung Sup YOON , Kyu Jun CHO
IPC: H01L27/12 , H01L21/84 , H01L21/683
Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes a substrate having a first region and a second region, a buffer layer disposed on the substrate, a semiconductor layer disposed on the buffer layer, a barrier layer disposed on the semiconductor layer, a first source electrode, a first drain electrode, and a first gate electrode disposed therebetween, which are disposed on the barrier layer in the first region, a second source electrode, a second drain electrode, and a second gate electrode disposed therebetween, which are disposed on the barrier layer in the second region, and a ferroelectric pattern interposed between the first gate electrode and the barrier layer.
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公开(公告)号：US20170236909A1
公开(公告)日：2017-08-17
申请号：US15248676
申请日：2016-08-26
Inventor： Ho Kyun AHN , Dong Min KANG , Yong-Hwan KWON , Dong-Young KIM , SEONG IL KIM , Hae Cheon KIM , Eun Soo NAM , Jae Won DO , Byoung-Gue MIN , Hyung Sup YOON , Sang-Heung LEE , Jong Min LEE , Jong-Won LIM , Hyun Wook JUNG , Kyu Jun CHO
IPC: H01L29/40 , H01L29/66 , H01L29/778 , H01L29/20 , H01L29/205
CPC classification number: H01L29/404 , H01L21/6835 , H01L29/0619 , H01L29/0657 , H01L29/2003 , H01L29/205 , H01L29/401 , H01L29/4175 , H01L29/66462 , H01L29/7786 , H01L29/7787 , H01L2221/68327 , H01L2221/6834
Abstract: A high electron mobility transistor includes a substrate including a first surface and a second surface facing each other and having a via hole passing through the first surface and the second surface, an active layer on the first surface, a cap layer on the active layer and including a gate recess region exposing a portion of the active layer, a source electrode and a drain electrode on one of the cap layer and the active layer, an insulating layer on the source electrode and the drain electrode and having on opening corresponding to the gate recess region to expose the gate recess region, a first field electrode on the insulating layer, a gate electrode electrically connected to the first field electrode on the insulating layer, and a second field electrode on the second surface and contacting the active layer through the via hole.
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公开(公告)号：US20170133471A1
公开(公告)日：2017-05-11
申请号：US15238492
申请日：2016-08-16
Inventor： Jong Min LEE , Byoung-Gue MIN , Hyung Sup YOON , Dong Min KANG , Dong-Young KIM , SEONG-IL KIM , Hae Cheon KIM , Jae Won DO , Ho Kyun AHN , Sang-Heung LEE , Jong-Won LIM , Hyun Wook JUNG , Kyu Jun CHO , Chull Won JU
IPC: H01L29/40 , H01L29/66 , H01L29/778 , H01L29/20 , H01L29/205
CPC classification number: H01L29/408 , H01L29/2003 , H01L29/205 , H01L29/66462 , H01L29/7786 , H01L29/7787
Abstract: The present invention relates to a high reliability field effect power device and a manufacturing method thereof. A method of manufacturing a field effect power device includes sequentially forming a transfer layer, a buffer layer, a barrier layer and a passivation layer on a substrate, patterning the passivation layer by etching a first region of the passivation layer, and forming at least one electrode on the first region of the barrier layer exposed by patterning the passivation layer, wherein the first region is provided to form the at least one electrode, and the passivation layer may include a material having a wider bandgap than the barrier layer to prevent a trapping effect and a leakage current of the field effect power device.
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