公开(公告)号：US20240222228A1

公开(公告)日：2024-07-04

申请号：US18089931

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Han Wui THEN ,  Wilfred GOMES ,  Anand S. MURTHY ,  Tahir GHANI ,  Sagar SUTHRAM ,  Pushkar RANADE

IPC: H01L23/48 ,  H01L21/02 ,  H01L23/00 ,  H01L23/498 ,  H01L23/522 ,  H01L25/065 ,  H01L27/088

CPC classification number: H01L23/481 ,  H01L21/02529 ,  H01L21/0254 ,  H01L21/0262 ,  H01L23/49827 ,  H01L23/5226 ,  H01L24/13 ,  H01L25/0657 ,  H01L27/088 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2924/05032 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/13091 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for semiconductor packages that use devices within an SiC layer coupled with devices within a GaN layer proximate to the SiC to convert a high voltage source to the package, e.g. greater than 1 kV, to 1-1.8 V used by components within the package. The devices may be transistors. The voltage conversion will allow increased power to be supplied to the package. Other embodiments may be described and/or claimed.

公开(公告)号：US20240222189A1

公开(公告)日：2024-07-04

申请号：US18162635

申请日：2023-01-31

Applicant: Powerchip Semiconductor Manufacturing Corporation

Inventor： Kuo Hsiung Chen ,  Ya-Ting Chen ,  Chun-Ta Chen ,  Chang Tsung Lin ,  Shih-Ping Lee

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76808 ,  H01L21/76813 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5226

Abstract: A manufacturing method of a semiconductor structure including the following steps is provided. A substrate is provided. A first dielectric layer is formed on the substrate. A first conductive layer is formed in the first dielectric layer. A capping layer is formed on the first dielectric layer and the first conductive layer. The material of the capping layer is nitride. A diffusion barrier layer covering the capping layer is formed. The material of the diffusion barrier layer is silicon-rich oxide (SRO). A second dielectric layer is formed on the diffusion barrier layer. An opening is formed in the second dielectric layer. The opening exposes the diffusion barrier layer. A patterned photoresist layer is formed on the second dielectric layer. A patterning process is performed by using the patterned photoresist layer as a mask to expand the opening and to expose the first conductive layer.

公开(公告)号：US12027498B2

公开(公告)日：2024-07-02

申请号：US17832019

申请日：2022-06-03

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay

IPC: H01L25/065 ,  H01L21/683 ,  H01L23/00 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/6835 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53228 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2224/11462 ,  H01L2224/11622 ,  H01L2224/13022 ,  H01L2224/13109 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2225/06586 ,  H01L2924/1431 ,  H01L2924/1434

Abstract: Semiconductor device package assemblies and associated methods are disclosed herein. In some embodiments, the semiconductor device package assembly includes (1) a base component having a front side and a back side opposite the first side, the base component having a first metallization structure at the front side, the first metallization structure being exposed in a contacting area at the front side; (2) a semiconductor device package having a first side and a second side, the semiconductor device package having a second metallization structure at the first side; and (3) a metal bump at least partially positioned in the recess and electrically coupled to the second metallization structure and the first metallization structure.

公开(公告)号：US12027482B2

公开(公告)日：2024-07-02

申请号：US17568355

申请日：2022-01-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonggi Jin ,  Gyuho Kang ,  Unbyoung Kang ,  Heewon Kim ,  Jumyong Park ,  Hyunsu Hwang

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L24/08 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/53238 ,  H01L24/05 ,  H01L2224/02251 ,  H01L2224/05009 ,  H01L2224/05555 ,  H01L2224/05647 ,  H01L2224/08146

Abstract: A semiconductor chip includes: a semiconductor substrate; a pad insulating layer on the semiconductor substrate; a through electrode which penetrates the semiconductor substrate and the pad insulating layer and includes a conductive plug and a conductive barrier layer surrounding a sidewall of the conductive plug; and a bonding pad which surrounds a sidewall of the through electrode and is spaced apart from the conductive plug with the conductive barrier layer disposed therebetween.

公开(公告)号：US12027460B2

公开(公告)日：2024-07-02

申请号：US17407449

申请日：2021-08-20

Applicant: Micron Technology, Inc.

Inventor： Adam W. Saxler

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L23/5283 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53266 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A microelectronic device comprises a stack structure, and slot structures vertically extending through the stack structure and dividing the stack structure into block structures. Each of the slot structures individually comprises an insulative liner material vertically extending through the slot structure and contacting sidewalls of the insulative levels and the conductive levels defining the slot structure, and grains of a material in contact with sidewalls of the insulative liner material. The grains of the material comprise first grains spanning an entire width between the sidewalls of the insulative liner material. Related memory devices, electronic systems, and methods are also described.

公开(公告)号：US12027415B2

公开(公告)日：2024-07-02

申请号：US17815177

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Che Chiang ,  Ju-Li Huang ,  Chun-Sheng Liang ,  Jeng-Ya Yeh

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/417 ,  H01L21/311

CPC classification number: H01L21/7682 ,  H01L21/76819 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76865 ,  H01L23/5226 ,  H01L23/5329 ,  H01L29/41775 ,  H01L21/31111 ,  H01L21/31116 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266

Abstract: In one exemplary aspect, a method for semiconductor manufacturing comprises forming first and second silicon nitride features on sidewall surfaces of a contact hole, where the contact hole is disposed in a dielectric layer and above a source/drain (S/D) feature. The method further comprises forming a contact plug in the contact hole, the contact plug being electrically coupled to the S/D feature, removing a top portion of the contact plug to create a recess in the contact hole, forming a hard mask layer in the recess, and removing the first and second silicon nitride features via selective etching to form first and second air gaps, respectively.

公开(公告)号：US20240215261A1

公开(公告)日：2024-06-27

申请号：US18596625

申请日：2024-03-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsiang-Ku Shen ,  Ku-Feng Lin ,  Liang-Wei Wang ,  Dian-Hau Chen

IPC: H10B61/00 ,  G11C11/16 ,  H01L23/522 ,  H01L23/528 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80

CPC classification number: H10B61/22 ,  G11C11/161 ,  H01L23/5226 ,  H01L23/5283 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80

Abstract: A semiconductor package includes a first integrated circuit and a second integrated circuit. The first integrated circuit includes a first semiconductor substrate, a first bonding structure bonded to the second integrated circuit, a ferromagnetic layer surrounding the first bonding structure, and a memory cell between the first semiconductor substrate and the first bonding structure.

公开(公告)号：US20240213223A1

公开(公告)日：2024-06-27

申请号：US18516367

申请日：2023-11-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaemok JUNG ,  Dowan KIM ,  Sungkeun PARK ,  Jongho PARK ,  Juil CHOI

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/522

CPC classification number: H01L25/0657 ,  H01L23/3107 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5226 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/08056 ,  H01L2224/08245 ,  H01L2224/16245 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/06544 ,  H01L2924/181

Abstract: A semiconductor package includes a first redistribution wiring layer having a first region and a second region surrounding the first region, a semiconductor chip disposed on the first region of the first redistribution wiring layer, a sealing member covering the semiconductor chip on the first redistribution wiring layer, vertical conductive wires penetrating the sealing member on the second region of the first redistribution wiring layer, a second redistribution wiring layer disposed on the sealing member and including second redistribution wirings electrically connected to the vertical conductive wires, and bonding pads provided on an upper surface of the first redistribution wiring layer or a lower surface of the second redistribution wiring layer, each bonding pad having a concavo-convex pattern on an upper surface of the bonding pad. The vertical conductive wires are bonded to the concavo-convex patterns of the bonding pads, respectively.

公开(公告)号：US20240213195A1

公开(公告)日：2024-06-27

申请号：US18174046

申请日：2023-02-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wei-De HO ,  Wei-Xiang YOU ,  Jui-Chien HUANG ,  Szuya LIAO

IPC: H01L23/00 ,  H01L23/522 ,  H01L25/065 ,  H01L25/07 ,  H01L27/088

CPC classification number: H01L24/08 ,  H01L23/5226 ,  H01L24/05 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/074 ,  H01L27/088 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/05676 ,  H01L2224/05684 ,  H01L2224/08145 ,  H01L2224/80357 ,  H01L2224/80379 ,  H01L2224/80896 ,  H01L2225/06541 ,  H01L2924/04642 ,  H01L2924/0504 ,  H01L2924/0544 ,  H01L2924/059

Abstract: A semiconductor structure includes a first device assembly and a second device assembly. Each of the first and second device assembly includes a substrate, a main unit disposed on the substrate and including at least one device, a dielectric unit disposed on the main unit and having an interconnecting surface opposite to the substrate, and an electrically conductive routing disposed in the dielectric unit, electrically connected to the at least one device, and including an end portion. The interconnecting surface of the dielectric unit of the first device assembly is bonded to the interconnecting surface of the dielectric unit of the second device assembly such that the end portion of the electrically conductive routing of the first device assembly is in direct contact with the end portion of the electrically conductive routing of the second device assembly. A method for manufacturing the semiconductor structure are also disclosed.

公开(公告)号：US20240213187A1

公开(公告)日：2024-06-27

申请号：US18534847

申请日：2023-12-11

Applicant: NEPES CO., LTD.

Inventor： JungWon LEE ,  InSoo KANG ,  Ju-Eok PARK ,  Se-Bin HWANG

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/15 ,  H01L23/31 ,  H01L23/498 ,  H01L23/522 ,  H01Q1/22

CPC classification number: H01L23/66 ,  H01L23/15 ,  H01L23/3107 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5226 ,  H01L24/08 ,  H01L24/16 ,  H01L24/94 ,  H01L24/97 ,  H01Q1/2283 ,  H01L2223/6677 ,  H01L2224/08225 ,  H01L2224/16225 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/181

Abstract: A semiconductor package and a manufacturing method thereof are disclosed. The semiconductor package and manufacturing method thereof according to an aspect of the present invention may include an antenna structure including a dielectric layer made of a transparent material, an active antenna pattern formed on one surface of the dielectric layer and a parasitic antenna pattern formed on the other surface of the dielectric layer opposite to the one surface; a first rewiring structure electrically connected to the active antenna pattern of the antenna structure; a molding body formed on one surface of the first rewiring structure; a semiconductor chip placed within the molding body; a second rewiring structure formed on one surface of the molding body; a vertical connection conductor laterally spaced from the semiconductor chip, penetrating the molding layer, and electrically connecting the second rewiring structure and the first rewiring structure; and an external connection terminal formed on one surface of the second rewiring structure.