公开(公告)号：US20240222189A1

公开(公告)日：2024-07-04

申请号：US18162635

申请日：2023-01-31

Applicant: Powerchip Semiconductor Manufacturing Corporation

Inventor： Kuo Hsiung Chen ,  Ya-Ting Chen ,  Chun-Ta Chen ,  Chang Tsung Lin ,  Shih-Ping Lee

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76808 ,  H01L21/76813 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5226

Abstract: A manufacturing method of a semiconductor structure including the following steps is provided. A substrate is provided. A first dielectric layer is formed on the substrate. A first conductive layer is formed in the first dielectric layer. A capping layer is formed on the first dielectric layer and the first conductive layer. The material of the capping layer is nitride. A diffusion barrier layer covering the capping layer is formed. The material of the diffusion barrier layer is silicon-rich oxide (SRO). A second dielectric layer is formed on the diffusion barrier layer. An opening is formed in the second dielectric layer. The opening exposes the diffusion barrier layer. A patterned photoresist layer is formed on the second dielectric layer. A patterning process is performed by using the patterned photoresist layer as a mask to expand the opening and to expose the first conductive layer.