公开(公告)号：US20230402460A1

公开(公告)日：2023-12-14

申请号：US18239241

申请日：2023-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： SUNGMIN KIM ,  Daewon Ha

IPC: H01L27/092 ,  H01L29/08 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L21/8238 ,  H01L23/522

CPC classification number: H01L27/0924 ,  H01L29/0847 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/42356 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823814 ,  H01L23/5226 ,  H01L21/02636

Abstract: A semiconductor device includes an active pattern including a channel region. The channel region is disposed between first and second source/drain patterns that are spaced apart from each other in a first direction. The channel region is configured to connect the first and second source/drain patterns to each other. A gate electrode is disposed on a bottom surface of the active pattern and is disposed between the first and second source/drain patterns. An upper interconnection line is disposed on a top surface of the active pattern opposite to the bottom surface of the active pattern and is connected to the first source/drain pattern.

公开(公告)号：US20230395601A1

公开(公告)日：2023-12-07

申请号：US18447407

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jhon Jhy Liaw

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L27/0924 ,  H01L21/823821 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/1037 ,  H01L29/0847

Abstract: The present disclosure provides an integrated circuit device that comprises a semiconductor substrate having a top surface; a first and a second source/drain features over the semiconductor substrate; a first semiconductor layer extending in parallel with the top surface and connecting the first and the second source/drain features, the first semiconductor layer having a center portion and two end portions, each of the two end portions connecting the center portion and one of the first and second source/drain features; a first spacer over the two end portions of the first semiconductor layer; a second spacer vertically between the two end portions of the first semiconductor layer and the top surface; and a gate electrode wrapping around and engaging the center portion of the first semiconductor layer. The center portion has a thickness smaller than the two end portions.

公开(公告)号：US20230387303A1

公开(公告)日：2023-11-30

申请号：US18446435

申请日：2023-08-08

Applicant: Peking University ,  Beijing Intellectual Property Operation Management Co., LTD

Inventor： Ming LI ,  Ran BI

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/775 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/7848 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/775 ,  H01L29/66439 ,  H01L21/823885 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/66545 ,  H01L29/78642 ,  H01L21/823814 ,  H01L21/823878

Abstract: A method for fabricating a vertical channel nanowire transistor with asymmetric stress distribution includes: (A) growing epitaxially a single-crystal material on a substrate; forming a laminate of a bottom source-drain material and a channel material; and generating a vertical uniaxial stress in the lightly-doped channel layer; (B) forming an inter-device isolation in an active layer; (C) forming a vertical channel by patterning; (D) depositing a dielectric layer to form a bottom gate isolation; (E) depositing a dummy gate layer followed by patterning to form a dummy gate pattern; (F) depositing a dielectric layer to form a top gate isolation; (G) patterning the top gate isolation; and forming a top source-drain by epitaxy growth; (H) removing a dummy gate; and forming a gate oxide layer and a metal gate; and (I) forming metal contact at individual ends of the device.

公开(公告)号：US20230387212A1

公开(公告)日：2023-11-30

申请号：US18360080

申请日：2023-07-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jhon Jhy Liaw

IPC: H01L29/10 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/786 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/1083 ,  H01L29/785 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/78696 ,  H01L29/0673 ,  H01L29/42392 ,  H01L27/0928 ,  H01L29/0638 ,  H01L21/823892 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/66545

Abstract: A metal-oxide semiconductor field effect transistor (MOSFET) includes a substrate and a well over the substrate, the well including dopants of a first conductivity-type. The well includes an anti-punch-through (APT) layer at an upper section of the well, the APT layer including the dopants of the first conductivity-type and further including carbon. The MOSFET further includes a source feature and a drain feature adjacent the APT layer, being of a second conductivity-type opposite to the first conductivity-type. The MOSFET further includes multiple channel layers over the APT layer and connecting the source feature to the drain feature, wherein the multiple channel layers are vertically stacked one over another. The MOSFET further includes a gate wrapping around each of the channel layers, such as in a gate-all-around device, wherein a first portion of the gate is disposed between a bottommost one of the channel layers and the APT layer.

公开(公告)号：US20230378365A1

公开(公告)日：2023-11-23

申请号：US18366392

申请日：2023-08-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Hao LIN ,  Chih-Chuan YANG ,  Chih-Hsuan CHEN ,  Bwo-Ning CHEN ,  Cha-Hon CHOU ,  Hsin-Wen SU ,  Chih-Hsiang HUANG

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/161 ,  H01L29/24 ,  H01L29/423 ,  H01L21/02 ,  H01L21/265 ,  H01L21/266 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/092

CPC classification number: H01L29/78618 ,  H01L29/0665 ,  H01L29/161 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/78696 ,  H01L21/0259 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/66742 ,  H01L27/092 ,  H01L21/2652 ,  H01L29/0673 ,  H10B10/125

Abstract: A method of fabricating a device includes providing a fin element in a device region and forming a dummy gate over the fin element. In some embodiments, the method further includes forming a source/drain feature within a source/drain region adjacent to the dummy gate. In some cases, the source/drain feature includes a bottom region and a top region contacting the bottom region at an interface interposing the top and bottom regions. In some embodiments, the method further includes performing a plurality of dopant implants into the source/drain feature. In some examples, the plurality of dopant implants includes implantation of a first dopant within the bottom region and implantation of a second dopant within the top region. In some embodiments, the first dopant has a first graded doping profile within the bottom region, and the second dopant has a second graded doping profile within the top region.

公开(公告)号：US20230378320A1

公开(公告)日：2023-11-23

申请号：US18181173

申请日：2023-03-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Fai Cheng ,  Chang-Miao Liu ,  Ming-Lung Cheng

IPC: H01L29/66 ,  H01L21/8238 ,  H01L29/775 ,  H01L29/06 ,  H01L29/786 ,  H01L29/423 ,  H01L27/092

CPC classification number: H01L29/66545 ,  H01L21/823814 ,  H01L21/823821 ,  H01L29/775 ,  H01L21/823878 ,  H01L29/0673 ,  H01L29/78696 ,  H01L29/42392 ,  H01L29/66439 ,  H01L27/0924

Abstract: A method includes forming a semiconductor fin protruding from a substrate, forming a dummy gate structure across the semiconductor fin, recessing the semiconductor fin in a region adjacent the dummy gate structure to form a recess, growing an epitaxial feature in the recess to fully covers an end of the semiconductor fin that is otherwise exposed in the recess, trimming the epitaxial feature to reduce a width of the epitaxial feature to expose again a portion of the end of the semiconductor fin in the recess, depositing a dielectric layer on the epitaxial feature and in physical contact with the exposed portion of the end of the semiconductor fin, and replacing the dummy gate structure with a metal gate structure.

公开(公告)号：US20230377989A1

公开(公告)日：2023-11-23

申请号：US18365832

申请日：2023-08-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hui-Lin Huang ,  Li-Li Su ,  Yee-Chia Yeo ,  Chii-Horng Li

IPC: H01L21/8238 ,  H01L29/45 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/033 ,  H01L21/285 ,  H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L21/823814 ,  H01L29/45 ,  H01L29/42392 ,  H01L29/78696 ,  H01L21/0259 ,  H01L21/0332 ,  H01L21/28518 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L29/66553 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66742 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/41733 ,  H01L29/78618

Abstract: A method includes etching a first recess adjacent a first dummy gate stack and a first fin; etching a second recess adjacent a second dummy gate stack and a second fin; and epitaxially growing a first epitaxy region in the first recess. The method further includes depositing a first metal-comprising mask over the first dummy gate stack, over the second dummy gate stack, over the first epitaxy region in the first recess, and in the second recess; patterning the first metal-comprising mask to expose the first dummy gate stack and the first epitaxy region; epitaxially growing a second epitaxy region in the first recess over the first epitaxy region; and after epitaxially growing the second epitaxy region, removing remaining portions of the first metal-comprising mask.

公开(公告)号：US11824057B2

公开(公告)日：2023-11-21

申请号：US17399222

申请日：2021-08-11

Applicant: Sony Corporation

Inventor： Koichi Matsumoto

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/49 ,  H01L29/423 ,  H01L29/417 ,  H01L21/28 ,  H01L29/06 ,  H01L29/08 ,  H01L29/51

CPC classification number: H01L27/0924 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28097 ,  H01L21/82385 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823864 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/42356 ,  H01L29/42376 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/4983 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/66545 ,  H01L29/66553

Abstract: A semiconductor device and method of making same. The semiconductor device includes: a first conductivity type transistor and a second conductivity type transistor, wherein each of the first conductivity type transistor and the second conductivity type includes a gate insulating film formed on a base, a metal gate electrode formed on the gate insulating film, and side wall spacers formed at side walls of the metal gate electrode, wherein the gate insulating film is made of a high dielectric constant material, and wherein offset spacers are formed between the side walls of the metal gate electrode and the inner walls of the side wall spacers in any one of the first conductivity type transistor and the second conductivity type transistor, or offset spacers having different thicknesses are formed in the first conductivity type transistor and the second conductivity type transistor.

公开(公告)号：US11823959B2

公开(公告)日：2023-11-21

申请号：US17406276

申请日：2021-08-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yi-Huan Chen ,  Chien-Chih Chou ,  Ta-Wei Lin ,  Hsiao-Chin Tuan ,  Alexander Kalnitsky ,  Kong-Beng Thei ,  Chia-Hong Wu

IPC: H01L21/8238 ,  H01L29/423 ,  H01L29/66 ,  H01L29/51 ,  H01L29/49 ,  H01L21/3105 ,  H01L29/08 ,  H01L21/3213 ,  H01L27/092 ,  H01L21/28 ,  H01L29/45

CPC classification number: H01L21/823835 ,  H01L21/28088 ,  H01L21/31053 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/823814 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/42372 ,  H01L29/45 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/665 ,  H01L29/66515 ,  H01L29/42364 ,  H01L29/517

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a gate dielectric structure over a substrate. A metal layer overlies the gate dielectric structure. A conductive layer overlies the metal layer. A polysilicon layer contacts opposing sides of the conductive layer. A bottom surface of the polysilicon layer is aligned with a bottom surface of the conductive layer. A dielectric layer overlies the polysilicon layer. The dielectric layer continuously extends from sidewalls of the polysilicon layer to an upper surface of the conductive layer.

公开(公告)号：US20230369332A1

公开(公告)日：2023-11-16

申请号：US18109296

申请日：2023-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung Soo Kim ,  Sung Min Kim

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L27/0922 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/775 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/66439

Abstract: There is provided a semiconductor device in which a shape of an isolation layer in a structure in which upper nanosheets are stacked on lower nanosheets is controlled to improve reliability of the device. The semiconductor device includes an active pattern on a substrate and extending in a first direction, lower nanosheets spaced apart from each other in a second direction intersecting the first direction and on the active pattern, an isolation layer on the lower nanosheets and spaced apart from the lower nanosheets in the second direction, upper nanosheets spaced apart from each other in the second direction and on the isolation layer, and a gate electrode on the substrate and surrounding each of the lower nanosheets, the isolation layer, and the upper nanosheets, wherein a sidewall of the isolation layer has a curved shape.