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    SEMICONDUCTOR DEVICES INCLUDING A STRESS PATTERN
    2.
    发明申请
    SEMICONDUCTOR DEVICES INCLUDING A STRESS PATTERN 有权

    公开(公告)号：US20220069128A1

    公开(公告)日：2022-03-03

    申请号：US17518741

    申请日：2021-11-04

    申请人： Samsung Electronics Co., Ltd.

    发明人： Sung Min Kim ,  Hyo Jin Kim ,  Dae Won Ha

    IPC分类号： H01L29/78 ,  H01L21/762

    摘要： Semiconductor devices are provided. A semiconductor device includes a fin structure including a stress structure and a semiconductor region that are sequentially stacked on a substrate. The semiconductor device includes a field insulation layer on a portion of the fin structure. The semiconductor device includes a gate electrode on the fin structure. Moreover, the stress structure includes an oxide.

    Semiconductor device and method for fabricating the same
    5.
    发明授权
    Semiconductor device and method for fabricating the same 有权

    公开(公告)号：US10181510B2

    公开(公告)日：2019-01-15

    申请号：US15726535

    申请日：2017-10-06

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Jung Gil Yang ,  Seung Min Song ,  Sung Min Kim ,  Woo Seok Park ,  Geum Jong Bae ,  Dong Il Bae

    IPC分类号： H01L29/76 ,  H01L29/06 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786

    摘要： A method of manufacturing a semiconductor device is provided. A stacked structure including one or more sacrificial layers and one or more semiconductor layers are stacked on a substrate is formed. A dummy gate structure including a dummy gate and a dummy spacer on the stacked structure is formed. The stacked structure is etched using the dummy gate structure to form a first recess. The one or more sacrificial layers are etched. The dummy spacer is removed. A spacer film is formed on the dummy gate, the one or more semiconductor layer and the one or more sacrificial layers. The semiconductor layer and spacer film are etched to form a second recess using the dummy gate and spacer film. An external spacer formed on the dummy gate and an internal spacer formed on the one or more sacrificial layers are formed. A source/drain region is formed in the second recess.

    Semiconductor device
    6.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US12080795B2

    公开(公告)日：2024-09-03

    申请号：US17517941

    申请日：2021-11-03

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Sung Min Kim

    IPC分类号： H01L29/78 ,  H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417

    CPC分类号： H01L29/785 ,  H01L23/5286 ,  H01L27/0886 ,  H01L29/0669 ,  H01L29/41791

    摘要： A semiconductor device includes a base substrate, a first electrode plate on the base substrate, a first power rail on the first electrode plate, the first power rail extending in a first horizontal direction and overlapping the first electrode plate in a vertical direction, a second power rail on the first electrode plate, the second power rail extending in the first horizontal direction and overlapping the first electrode plate in the vertical direction, and the second power rail being spaced apart from the first power rail in a second horizontal direction different from the first horizontal direction, a first power rail contact electrically connecting the first electrode plate and the first power rail, an insulating layer on the base substrate to surround the first electrode plate, the first power rail, and the second power rail, and a gate electrode extending in the second horizontal direction on the insulating layer.

    Semiconductor device
    9.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US10748897B2

    公开(公告)日：2020-08-18

    申请号：US16372534

    申请日：2019-04-02

    申请人： Samsung Electronics Co., Ltd.

    发明人： Sung Min Kim ,  Dong Won Kim

    IPC分类号： H01L27/088 ,  H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/768

    摘要： A semiconductor device is provided, which includes a first and second multichannel active patterns spaced apart from one another and extending in a first direction. The semiconductor device also includes first and second gate structures on the first and second multichannel active patterns, extending in a second direction and including first and second gate insulating films, respectively. Sidewalls of the first multichannel active pattern include first portions in contact with the first gate insulating film, second portions not in contact with the first gate insulating film, third portions in contact with the second gate insulating film, and fourth portions not in contact with the second gate insulating film. Additionally, a height of the first portions of the first multichannel active pattern is greater than a height of the third portions of the first multichannel active pattern.