公开(公告)号：US20150361303A1

公开(公告)日：2015-12-17

申请号：US14797294

申请日：2015-07-13

Applicant: Hitachi Chemical Company, Ltd.

Inventor： Yousuke HOSHI ,  Daisuke Ryuzaki ,  Naoyuki Koyama ,  Shigeru Nobe

IPC: C09G1/02 ,  H01L21/762 ,  H01L21/3105

CPC classification number: C09G1/02 ,  B24B37/044 ,  C09K3/1463 ,  H01L21/30625 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/76224

Abstract: Disclosed is a polishing agent comprising: water; tetravalent metal hydroxide particles; and an additive, wherein the additive contains at least one of a cationic polymer and a cationic polysaccharide. The present invention can provide a polishing agent which is capable of polishing an insulating film at a high speed with less polishing flaws, and having a high polishing rate ratio of a silicon oxide film and a stopper film, in the CMP technology of flattening insulating film. The present invention can also provide a polishing agent set for storing the polishing agent, and a method for polishing a substrate using this polishing agent.

Abstract translation: 公开了一种抛光剂，其包括：水; 四价金属氢氧化物颗粒; 和添加剂，其中所述添加剂含有阳离子聚合物和阳离子多糖中的至少一种。 本发明可以提供一种抛光剂，其能够在平坦化绝缘膜的CMP技术中以高速抛光较少的抛光缺陷并且具有高的氧化硅膜和阻挡膜的抛光速率比的抛光剂 。 本发明还可以提供用于储存抛光剂的抛光剂组，以及使用该研磨剂研磨基材的方法。

公开(公告)号：US20150357283A1

公开(公告)日：2015-12-10

申请号：US14828986

申请日：2015-08-18

Applicant: International Business Machines Corporation ,  Hitachi Chemcial DuPont Microsystems, L.L.C.

Inventor： Paul S. Andry ,  Sarah H. Knickerbocker ,  Ron R. Legario ,  Cornelia K. Tsang ,  Melvin P. Zussman

IPC: H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/02118 ,  H01L21/02274 ,  H01L21/31055 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/481 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/5329 ,  H01L2224/13

Abstract: A method of forming an integrated circuit assembly includes forming an insulator layer on a preliminary semiconductor assembly. The preliminary semiconductor assembly includes a semiconductor substrate having a first side and a second side opposite the first side, a semiconductor circuitry layer formed on the first side of the semiconductor substrate, and a conductive via extending through the semiconductor substrate from the semiconductor circuitry layer to the second side. The insulator is formed on the second side and an end of the conductive via. The method includes forming a polymer layer on the insulator layer, removing a quantity of the polymer layer sufficient to expose the end of the conductive via through the insulator layer, and forming a conductive contact on the polymer layer and the end of the conductive via.

Abstract translation: 形成集成电路组件的方法包括在初步半导体组件上形成绝缘体层。 初步半导体组件包括具有第一侧和与第一侧相对的第二侧的半导体衬底，形成在半导体衬底的第一侧上的半导体电路层和从半导体电路层延伸穿过半导体衬底的导电通孔 第二面。 绝缘体形成在导电通孔的第二侧和端部上。 该方法包括在绝缘体层上形成聚合物层，除去一定量的聚合物层，足以暴露导电通孔的端部穿过绝缘体层，以及在聚合物层和导电通孔的末端上形成导电接触。

公开(公告)号：US09209128B2

公开(公告)日：2015-12-08

申请号：US14231816

申请日：2014-04-01

Applicant: International Business Machines Corporation ,  Hitachi Chemical DuPont Microsystems, L.L.C.

Inventor： Paul S. Andry ,  Sarah H. Knickerbocker ,  Ron R. Legario ,  Cornelia K. Tsang ,  Melvin P. Zussman

IPC: H01L21/20 ,  H01L21/4763 ,  H01L21/44 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L21/3105 ,  H01L21/02

CPC classification number: H01L23/5226 ,  H01L21/02118 ,  H01L21/02274 ,  H01L21/31055 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/481 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/5329 ,  H01L2224/13

Abstract: A method of forming an integrated circuit assembly includes forming an insulator layer on a preliminary semiconductor assembly. The preliminary semiconductor assembly includes a semiconductor substrate having a first side and a second side opposite the first side, a semiconductor circuitry layer formed on the first side of the semiconductor substrate, and a conductive via extending through the semiconductor substrate from the semiconductor circuitry layer to the second side. The insulator is formed on the second side and an end of the conductive via. The method includes forming a polymer layer on the insulator layer, removing a quantity of the polymer layer sufficient to expose the end of the conductive via through the insulator layer, and forming a conductive contact on the polymer layer and the end of the conductive via.

Abstract translation: 形成集成电路组件的方法包括在初步半导体组件上形成绝缘体层。 初步半导体组件包括具有第一侧和与第一侧相对的第二侧的半导体衬底，形成在半导体衬底的第一侧上的半导体电路层和从半导体电路层延伸穿过半导体衬底的导电通孔 第二面。 绝缘体形成在导电通孔的第二侧和端部上。 该方法包括在绝缘体层上形成聚合物层，除去一定量的聚合物层，足以暴露导电通孔的端部穿过绝缘体层，以及在聚合物层和导电通孔的末端上形成导电接触。

公开(公告)号：US20150340475A1

公开(公告)日：2015-11-26

申请号：US14819654

申请日：2015-08-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chien-Chih LIN ,  Long-Jie HONG ,  Chih-Lin WANG ,  Chia-Der CHANG

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/3105 ,  H01L21/311

CPC classification number: H01L29/66795 ,  H01L21/31055 ,  H01L21/311 ,  H01L21/31144 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

Abstract: A method for manufacturing a semiconductor device includes forming two isolation structures in a substrate to define a fin structure between the two isolation structures in the substrate. A dummy gate and spacers are formed bridging the two isolation structures and over the fin structure. The two isolation structures are etched with the dummy gate and the spacers as a mask to form a plurality of slopes under the spacers in the two isolation structures. A gate etch stop layer is formed overlying the plurality of slopes. The dummy gate and the two isolation structures beneath the dummy gate are removed to create a cavity confined by the spacers and the gate etch stop layer. A gate is then formed in the cavity.

Abstract translation: 一种用于制造半导体器件的方法包括在衬底中形成两个隔离结构以在衬底中的两个隔离结构之间限定翅片结构。 形成虚拟栅极和间隔物，桥接两个隔离结构和鳍状结构。 用虚拟栅极和间隔物作为掩模蚀刻两个隔离结构，以在两个隔离结构中的间隔物下方形成多个斜面。 在多个斜面上形成栅极蚀刻停止层。 去除虚拟栅极和虚拟栅极之下的两个隔离结构以产生由间隔物和栅极蚀刻停止层限制的空腔。 然后在空腔中形成栅极。

公开(公告)号：US20150333148A1

公开(公告)日：2015-11-19

申请号：US14660191

申请日：2015-03-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungbum KOO ,  Seungjae Lee ,  Shinhye Kim ,  Zulkarnain ,  Narae Oh ,  Jeong-Kyu Lee

IPC: H01L29/66 ,  H01L21/283 ,  H01L21/31 ,  H01L21/3105 ,  H01L23/528 ,  H01L21/3213 ,  H01L21/768 ,  H01L29/78 ,  H01L27/11 ,  H01L29/423 ,  H01L21/311

CPC classification number: H01L29/66545 ,  H01L21/283 ,  H01L21/31 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/32133 ,  H01L21/768 ,  H01L21/76897 ,  H01L23/528 ,  H01L27/1104 ,  H01L29/165 ,  H01L29/4232 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices and methods of manufacturing the semiconductor devices are provided. The methods may include forming a sacrificial gate pattern on a substrate, forming a first spacer on a sidewall of the sacrificial gate pattern and forming a first interlayer dielectric (ILD) layer covering a sidewall of the first spacer and exposing a top surface of the first spacer. The first spacer may expose an upper portion of the sidewall of the sacrificial gate pattern. The methods may also include forming a capping insulating pattern covering top surfaces of the first spacer and the first ILD layer, replacing the sacrificial gate pattern with a gate electrode structure and patterning the capping insulating pattern to form a second spacer on the first spacer and between the gate electrode structure and the first ILD layer. The second spacer may be formed of a material having a dielectric constant higher than a dielectric constant of the first spacer.

Abstract translation: 提供了制造半导体器件的半导体器件和方法。 所述方法可以包括在衬底上形成牺牲栅极图案，在牺牲栅极图案的侧壁上形成第一间隔物，并形成覆盖第一间隔物的侧壁的第一层间电介质（ILD）层，并暴露第一间隔物的顶表面 间隔 第一间隔物可以暴露牺牲栅极图案的侧壁的上部。 所述方法还可以包括形成覆盖第一间隔物和第一ILD层的顶表面的封盖绝缘图案，用栅极电极结构代替牺牲栅极图案，并且图案化封盖绝缘图案以在第一间隔物上形成第二间隔物， 栅电极结构和第一ILD层。 第二间隔物可以由具有高于第一间隔物的介电常数的介电常数的材料形成。

公开(公告)号：US09184263B2

公开(公告)日：2015-11-10

申请号：US14143468

申请日：2013-12-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiuyu Cai ,  Ajey Poovannummoottil Jacob ,  Daniel T. Pham ,  Mark V. Raymond ,  Christopher M. Prindle ,  Catherine B. Labelle ,  Linus Jang ,  Robert Teagle

IPC: H01L21/3205 ,  H01L29/66 ,  H01L21/3105 ,  H01L29/06 ,  H01L29/417 ,  H01L29/51 ,  H01L29/423 ,  H01L21/768 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L21/31055 ,  H01L21/76897 ,  H01L29/0692 ,  H01L29/4175 ,  H01L29/41791 ,  H01L29/42364 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7843 ,  H01L29/785 ,  H01L29/7851

Abstract: One method disclosed herein includes, among other things, forming sidewall spacers adjacent opposite sides of a sacrificial gate electrode of a sacrificial gate structure, forming a tensile-stressed layer of insulating material adjacent the sidewall spacers, removing the sacrificial gate structure to define a replacement gate cavity positioned between the sidewall spacers, forming a replacement gate structure in the replacement gate cavity, forming a tensile-stressed gate cap layer above the replacement gate structure and within the replacement gate cavity and, after forming the tensile-stressed gate cap layer, removing the tensile-stressed layer of insulating material.

Abstract translation: 本文公开的一种方法尤其包括邻近牺牲栅极结构的牺牲栅电极的相对侧的侧壁间隔壁，形成邻近侧壁间隔物的绝缘材料的拉应力层，去除牺牲栅极结构以限定替换 门腔定位在侧壁间隔件之间，在置换栅腔中形成替换栅极结构，在置换栅极结构之上和置换栅极腔内形成拉伸应力栅极盖层，并且在形成拉伸应力栅极盖层之后， 去除绝缘材料的拉应力层。

公开(公告)号：US20150279779A1

公开(公告)日：2015-10-01

申请号：US14231816

申请日：2014-04-01

Applicant: Hitachi Chemical DuPont Microsystems, L.L.C. ,  International Business Machines Corporation

Inventor： Paul S. Andry ,  Sarah H. Knickerbocker ,  Ron R. Legario ,  Cornelia K. Tsang ,  Melvin P. Zussman

IPC: H01L23/522 ,  H01L21/02 ,  H01L21/768 ,  H01L21/3105 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/02118 ,  H01L21/02274 ,  H01L21/31055 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/481 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/5329 ,  H01L2224/13

Abstract: A method of forming an integrated circuit assembly includes forming an insulator layer on a preliminary semiconductor assembly. The preliminary semiconductor assembly includes a semiconductor substrate having a first side and a second side opposite the first side, a semiconductor circuitry layer formed on the first side of the semiconductor substrate, and a conductive via extending through the semiconductor substrate from the semiconductor circuitry layer to the second side. The insulator is formed on the second side and an end of the conductive via. The method includes forming a polymer layer on the insulator layer, removing a quantity of the polymer layer sufficient to expose the end of the conductive via through the insulator layer, and forming a conductive contact on the polymer layer and the end of the conductive via.

公开(公告)号：US20150274757A1

公开(公告)日：2015-10-01

申请号：US14681416

申请日：2015-04-08

Applicant: Board of Regents, The University of Texas System

Inventor： C. Grant Willson ,  Tsuyoshi Ogawa ,  Michael B. Jacobsson

IPC: C07F7/08

CPC classification number: C07F7/0881 ,  C07D301/00 ,  C07D303/12 ,  C07F7/0838 ,  C07F7/0874 ,  C07F7/0878 ,  C07F7/0879 ,  C07F7/0889 ,  C07F7/0896 ,  C09D163/00 ,  G03F7/0002 ,  H01L21/31055

Abstract: The present invention describes branched and functionalized siloxanes and methods for making such compounds. The compounds have a variety of uses. One preferred application is as novel planarizing material for lithography, in which case functionalized branched siloxane, such as an epoxy-modified branched siloxane is particularly useful.

Abstract translation: 本发明描述了支链和官能化硅氧烷及其制备方法。 这些化合物具有多种用途。 一种优选的应用是用于光刻的新型平面化材料，在这种情况下，官能化的支化硅氧烷，例如环氧改性的支化硅氧烷是特别有用的。

公开(公告)号：US20150262883A1

公开(公告)日：2015-09-17

申请号：US14722597

申请日：2015-05-27

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu ,  Jun Luo ,  Chunlong Li ,  Jian Deng ,  Chao Zhao

IPC: H01L21/8234 ,  H01L21/265 ,  H01L21/321 ,  H01L29/66 ,  H01L21/306 ,  H01L21/308 ,  H01L21/3105 ,  H01L29/10

CPC classification number: H01L21/823431 ,  H01L21/265 ,  H01L21/30604 ,  H01L21/3083 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31056 ,  H01L21/31105 ,  H01L21/32115 ,  H01L21/32132 ,  H01L21/76229 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/1083 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/6681 ,  H01L29/7848

Abstract: A planarization process is disclosed. The method includes forming a trench in an area of a material layer which has a relatively high loading condition for sputtering. The method further includes sputtering the material layer to make the material layer flat.

Abstract translation: 公开了平面化处理。 该方法包括在具有相对高的溅射负载条件的材料层的区域中形成沟槽。 该方法还包括溅射材料层以使材料层平坦。

公开(公告)号：US20150262868A1

公开(公告)日：2015-09-17

申请号：US14213051

申请日：2014-03-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Yuan Ting ,  Jyu-Horng Shieh

IPC: H01L21/768 ,  H01L23/48 ,  H01L29/78

CPC classification number: H01L21/76892 ,  H01L21/0274 ,  H01L21/0337 ,  H01L21/31055 ,  H01L21/32115 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/7682 ,  H01L21/76837 ,  H01L21/7684 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/481 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method includes forming a metallic layer over a Metal-Oxide-Semiconductor (MOS) device, forming reverse memory posts over the metallic layer, and etching the metallic layer using the reverse memory posts as an etching mask. The remaining portions of the metallic layer include a gate contact plug and a source/drain contact plug. The reverse memory posts are then removed. After the gate contact plug and the source/drain contact plug are formed, an Inter-Level Dielectric (ILD) is formed to surround the gate contact plug and the source/drain contact plug.

Abstract translation: 一种方法包括在金属氧化物半导体（MOS）器件上形成金属层，在金属层上形成反向存储器柱，并使用反向存储器柱作为蚀刻掩模蚀刻金属层。 金属层的其余部分包括栅极接触插塞和源极/漏极接触插塞。 然后删除反向内存条。 在形成栅极接触插塞和源极/漏极接触插塞之后，形成级间介质（ILD）以围绕栅极接触插塞和源极/漏极接触插塞。