公开(公告)号：US20240170339A1

公开(公告)日：2024-05-23

申请号：US18116713

申请日：2023-03-02

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Te-Chih Hsiung ,  Yun-Hua Chen ,  Yang-Cheng Wu ,  Sheng-Hsun Fu ,  Wen-Kuo Hsieh ,  Chih-Yuan Ting ,  Huan-Just Lin ,  Bing-Sian Wu ,  Yi-Hsuan Chiu

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

摘要： In a method of manufacturing a semiconductor device, an n-type source/drain epitaxial layer and a p-type source/drain epitaxial layer respectively formed, a dielectric layer is formed over the n-type source/drain epitaxial layer and the p-type source/drain epitaxial layer, a first opening is formed in the dielectric layer to expose a part of the n-type source/drain epitaxial layer and a second opening is formed in the dielectric layer to expose a part of the p-type source/drain epitaxial layer, and the n-type source/drain epitaxial layer and the p-type source/drain epitaxial layer respectively recessed. A recessing amount of the n-type source/drain epitaxial layer is different from a recessing amount of the p-type source/drain epitaxial layer.

公开(公告)号：US11101429B2

公开(公告)日：2021-08-24

申请号：US16371784

申请日：2019-04-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tai-Yen Peng ,  Sin-Yi Yang ,  Chen-Jung Wang ,  Yu-Shu Chen ,  Chien Chung Huang ,  Han-Ting Lin ,  Jyu-Horng Shieh ,  Chih-Yuan Ting

IPC分类号： H01L43/12 ,  H01L27/22 ,  H01L43/02

摘要： A method of forming integrated circuits includes forming Magnetic Tunnel Junction (MTJ) stack layers, depositing a conductive etch stop layer over the MTJ stack layers, depositing a conductive hard mask over the conductive etch stop layer, and patterning the conductive hard mask to form etching masks. The patterning is stopped by the conductive etch stop layer. The method further includes etching the conducive etch stop layer using the etching masks to define patterns, and etching the MTJ stack layers to form MTJ stacks.

公开(公告)号：US20200043851A1

公开(公告)日：2020-02-06

申请号：US16600171

申请日：2019-10-11

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Yuan Ting

IPC分类号： H01L23/528 ,  H01L21/768 ,  H01L23/532

摘要： An interconnect and a method of forming an interconnect for a semiconductor device is provided. Conductive lines having different widths are formed. Wider conductive lines are used where the design includes an overlying via, and narrower lines are used in which an overlying via is not included. An overlying dielectric layer is formed and trenches and vias are formed extending through the overlying dielectric layer to the wider conductive lines. Voids or air gaps may be formed adjacent select conductive lines, such as the narrower lines.

公开(公告)号：US10535556B2

公开(公告)日：2020-01-14

申请号：US16218591

申请日：2018-12-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Yuan Ting ,  Jyu-Horng Shieh ,  Pei-Wen Huang

IPC分类号： H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/033 ,  H01L23/528 ,  H01L23/485 ,  H01L23/532

摘要： A semiconductor device is disclosed, including a plurality of conductive features disposed over a substrate. A dielectric layer separates the conductive features. A conductive line is provided, connecting a subset of the conductive features. The conductive line includes a line-like portion and a line-end portion.

公开(公告)号：US10269632B2

公开(公告)日：2019-04-23

申请号：US15463929

申请日：2017-03-20

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ming-Hui Chu ,  Chih-Yuan Ting ,  Jyu-Horng Shieh

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L21/311 ,  H01L23/532 ,  H01L23/528

摘要： A method of forming a semiconductor device is provided. Metallic interconnects are formed in a dielectric layer of the semiconductor device. A hard mask is used to avoid usual problems faced by manufacturers, such as possibility of bridging different conductive elements and via patterning problems when there are overlays between vias and trenches. The hard mask is etched multiple times to extend via landing windows, while keeping distance between the conductive elements to avoid the bridging problem.

公开(公告)号：US20190067090A1

公开(公告)日：2019-02-28

申请号：US16172990

申请日：2018-10-29

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jeng-Shiou Chen ,  Chih-Yuan Ting

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L21/76829 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

摘要： An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); a middle low-k (LK) dielectric layer over the lower ESL; a supporting layer over the middle LK dielectric layer; an upper LK dielectric layer over the supporting layer; an upper conductive feature in the upper LK dielectric layer, wherein the upper conductive feature is through the supporting layer; a gap along an interface of the upper conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the upper conductive feature, and the gap.

公开(公告)号：US10043754B2

公开(公告)日：2018-08-07

申请号：US15350689

申请日：2016-11-14

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Yuan Ting ,  Jyu-Horng Shieh

IPC分类号： H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L21/764 ,  H01L23/528

CPC分类号： H01L23/53295 ,  H01L21/764 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76852 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A device having a conductive feature disposed on a substrate; a cap structure is disposed on top of the conductive feature and on at least two sidewalls of the conductive feature. An air gap cap disposed on the cap structure and defines an air gap adjacent the conductive feature.

公开(公告)号：US09929094B2

公开(公告)日：2018-03-27

申请号：US15430189

申请日：2017-02-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Yuan Ting ,  Jyu-Horng Shieh

IPC分类号： H01L23/48 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L21/311 ,  H01L23/522

CPC分类号： H01L23/5283 ,  H01L21/31144 ,  H01L21/764 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76879 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5228 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A device including a first conductive feature and a second conductive feature having a coplanar top surface where the conductive features are disposed a first distance apart at the coplanar top surface. A trench filled with air interposes the first and second conductive features. The trench has a first width at a region coplanar with the top surface of the first and second conductive features. The first width is less than the first distance. A dielectric layer is disposed over the first and second conductive features and the trench; the dielectric layer provides a cap for the trench filled with air.

公开(公告)号：US20170178951A1

公开(公告)日：2017-06-22

申请号：US15443159

申请日：2017-02-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chih-Yuan Ting

IPC分类号： H01L21/768 ,  H01L23/528 ,  H01L23/522

CPC分类号： H01L21/76807 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/7681 ,  H01L21/76811 ,  H01L21/76814 ,  H01L21/76816 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76835 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit structure includes a first dielectric layer, an etch stop layer over the first dielectric layer, and a second dielectric layer over the etch stop layer. A via is disposed in the first dielectric layer and the etch stop layer. A metal line is disposed in the second dielectric layer, wherein the metal line is connected to the via. The etch stop layer includes a first portion having an edge contacting an edge of the via, wherein the first portion has a first chemical composition, and a second portion in contact with the first portion. The second portion is spaced apart from the via by the first portion, and wherein the second portion has a second chemical composition different from the first composition.

公开(公告)号：US20170148735A1

公开(公告)日：2017-05-25

申请号：US15425778

申请日：2017-02-06

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Yuan Ting

IPC分类号： H01L23/528 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L23/5283 ,  H01L21/76811 ,  H01L21/7682 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect and a method of forming an interconnect for a semiconductor device is provided. Conductive lines having different widths are formed. Wider conductive lines are used where the design includes an overlying via, and narrower lines are used in which an overlying via is not included. An overlying dielectric layer is formed and trenches and vias are formed extending through the overlying dielectric layer to the wider conductive lines. Voids or air gaps may be formed adjacent select conductive lines, such as the narrower lines.