公开(公告)号：US20190156895A1

公开(公告)日：2019-05-23

申请号：US16260026

申请日：2019-01-28

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Xiao LU ,  Xiaonan CHEN ,  Zhongze WANG

IPC: G11C16/10 ,  G11C17/14 ,  H01L27/112 ,  H01L29/792 ,  G11C16/04 ,  G11C17/18 ,  G11C17/16 ,  H01L29/423

Abstract: A semiconductor device for a one-time programmable (OTP) memory according to some examples of the disclosure includes a gate, a dielectric region below the gate, a source terminal below the dielectric region and offset to one side, a drain terminal below the dielectric region and offset to an opposite side from the source terminal, a drain side charge trap in the dielectric region capable of programming the semiconductor device, and a source side charge trap in the dielectric region opposite the drain side charge trap and capable of programming the semiconductor device.

公开(公告)号：US20190088765A1

公开(公告)日：2019-03-21

申请号：US16196384

申请日：2018-11-20

Applicant: QUALCOMM Incorporated

Inventor： Bin YANG ,  Gengming TAO ,  Xia LI ,  Periannan CHIDAMBARAM

IPC: H01L29/66 ,  H01L21/768 ,  H01L29/423 ,  H01L29/40 ,  H01L29/778 ,  H01L21/285 ,  H01L29/47 ,  H01L29/812 ,  H01L29/20

Abstract: A compound semiconductor field effect transistor (FET) may include a channel layer. The semiconductor FET may also include an oxide layer, partially surrounded by a passivation layer, on the channel layer. The semiconductor FET may also include a first dielectric layer on the oxide layer. The semiconductor FET may also include a second dielectric layer on the first dielectric layer. The semiconductor FET may further include a gate, comprising a base gate through the oxide layer and the first dielectric layer, and a head gate in the second dielectric layer and electrically coupled to the base gate.

公开(公告)号：US20190013398A1

公开(公告)日：2019-01-10

申请号：US15645188

申请日：2017-07-10

Applicant: QUALCOMM Incorporated

Inventor： Bin YANG ,  Xia LI ,  Gengming TAO ,  Periannan CHIDAMBARAM

IPC: H01L29/778 ,  H01L29/10 ,  H01L29/205 ,  H01L29/66 ,  H01L21/74 ,  H01L23/66

Abstract: A compound semiconductor field effect transistor may include a channel layer. The compound semiconductor transistor may also include a multi-layer epitaxial barrier layer on the channel layer. The channel layer may be on a doped buffer layer or on a first un-doped buffer layer. The compound semiconductor field effect transistor may further include a gate. The gate may be on a first tier of the multi-layer epitaxial barrier layer, and through a space between portions of a second tier of the multi-layer epitaxial barrier layer.

公开(公告)号：US20180277657A1

公开(公告)日：2018-09-27

申请号：US15683530

申请日：2017-08-22

Applicant: QUALCOMM Incorporated

Inventor： Bin YANG ,  Gengming TAO ,  Xia LI ,  Periannan CHIDAMBARAM

IPC: H01L29/66 ,  H01L29/40 ,  H01L29/423 ,  H01L29/778 ,  H01L21/768

CPC classification number: H01L29/66621 ,  H01L21/28581 ,  H01L21/28587 ,  H01L21/76822 ,  H01L29/20 ,  H01L29/402 ,  H01L29/42312 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/475 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66553 ,  H01L29/66575 ,  H01L29/778 ,  H01L29/7787 ,  H01L29/812 ,  H01L29/8128

Abstract: A compound semiconductor field effect transistor (FET) may include a channel layer. The semiconductor FET may also include an oxide layer, partially surrounded by a passivation layer, on the channel layer. The semiconductor FET may also include a first dielectric layer on the oxide layer. The semiconductor FET may also include a second dielectric layer on the first dielectric layer. The semiconductor FET may further include a gate, comprising a base gate through the oxide layer and the first dielectric layer, and a head gate in the second dielectric layer and electrically coupled to the base gate.

公开(公告)号：US20180247933A1

公开(公告)日：2018-08-30

申请号：US15587837

申请日：2017-05-05

Applicant: QUALCOMM Incorporated

Inventor： Bin YANG ,  Xia LI ,  Gengming TAO

IPC: H01L27/06 ,  H01L49/02 ,  H01L29/778 ,  H01L29/737 ,  H01L29/20 ,  H01L23/532 ,  H01L23/535 ,  H01L21/8252 ,  H01L21/768 ,  H01L23/66

CPC classification number: H01L27/0605 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76895 ,  H01L21/8252 ,  H01L23/5227 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/535 ,  H01L23/66 ,  H01L28/10 ,  H01L28/40 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/737 ,  H01L29/7786 ,  H01L2223/6616 ,  H01L2223/6672 ,  H01L2223/6677

Abstract: An integrated compound semiconductor circuit including a high-Q passive device may include a compound semiconductor transistor. The integrated compound semiconductor circuity may also include a high-Q inductor device. The integrated compound semiconductor may further include a back-end-of-line interconnect layer electrically contacting the high-Q inductor device and the compound semiconductor transistor, the back-end-of-line interconnect layer comprising a gold base layer and a copper interconnect layer.

公开(公告)号：US20180211897A1

公开(公告)日：2018-07-26

申请号：US15597386

申请日：2017-05-17

Applicant: QUALCOMM Incorporated

Inventor： Bin YANG ,  Gengming TAO ,  Xia LI

IPC: H01L23/367 ,  H01L29/737 ,  H01L29/205 ,  H01L29/225 ,  H01L29/66

CPC classification number: H01L29/66969 ,  H01L23/3677 ,  H01L29/0821 ,  H01L29/205 ,  H01L29/225 ,  H01L29/41708 ,  H01L29/66318 ,  H01L29/7371

Abstract: A heterojunction bipolar transistor may include an emitter, a base contacting the emitter, a collector contacting the base, a sub-collector contacting the collector, and an electrical isolation layer contacting the sub-collector. The heterojunction bipolar transistor may also include a backside heatsink thermally coupled to the sub-collector and the collector. The backside heatsink may be aligned with a central axis of the emitter and the base.

公开(公告)号：US20160329488A1

公开(公告)日：2016-11-10

申请号：US15213384

申请日：2016-07-18

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Yu LU ,  Seung Hyuk KANG

IPC: H01L43/02 ,  H01L43/12 ,  H01L43/08

CPC classification number: H01L43/02 ,  G11C11/161 ,  G11C11/1659 ,  H01L27/222 ,  H01L43/08 ,  H01L43/12

Abstract: A magnetoresistive random-access memory (MRAM) integration compatible with shrinking device technologies includes a magnetic tunnel junction (MTJ) formed in a common interlayer metal dielectric (IMD) layer with one or more logic elements. The MTJ is connected to a bottom metal line in a bottom IMD layer and a top via connected to a top IMD layer. The MTJ substantially extends between one or more bottom cap layers configured to separate the common IMD layer and the bottom IMD layer and one or more top cap layers configured to separate the common IMD layer and the top IMD layer. The MTJ can include a top electrode to connect to the top via or be directly connected to the top via through a hard mask for smaller device technologies. The logic elements include vias, metal lines, and semiconductor devices.

Abstract translation: 与收缩装置技术兼容的磁阻随机存取存储器（MRAM）集成包括形成在具有一个或多个逻辑元件的公共夹层金属电介质（IMD）层中的磁性隧道结（MTJ）。 MTJ连接到底部IMD层中的底部金属线和连接到顶部IMD层的顶部通孔。 MTJ基本上在配置成分离公共IMD层和底部IMD层的一个或多个底盖层之间延伸，以及被配置为分离公共IMD层和顶部IMD层的一个或多个顶盖层。 MTJ可以包括顶部电极，以连接到顶部通孔，或者通过用于较小器件技术的硬掩模直接连接到顶部通孔。 逻辑元件包括通孔，金属线和半导体器件。

公开(公告)号：US20160093668A1

公开(公告)日：2016-03-31

申请号：US14496525

申请日：2014-09-25

Applicant: QUALCOMM Incorporated

Inventor： Yu LU ,  Xia LI ,  Seung Hyuk KANG

IPC: H01L27/22 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L45/02 ,  H01L45/00

CPC classification number: H01L27/222 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L43/08 ,  H01L43/12 ,  H01L45/02 ,  H01L45/08 ,  H01L45/12 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Systems and methods of integration of resistive memory elements with logic elements in advanced nodes with improved mechanical stability and reduced parasitic capacitance include a resistive memory element and a logic element formed in a common integration layer extending between a bottom cap layer and a top cap layer. At least a first intermetal dielectric (IMD) layer of high-K value is formed in the common integration layer and surrounding at least the resistive memory element, to provide high rigidity and mechanical stability. A second IMD layer of low-K value to reduce parasitic capacitance of the logic element is formed in either the common integration layer, a top layer above the top cap layer or an intermediate layer in between the top and bottom cap layers. Air gaps may be formed in one or more IMD layers to further reduce capacitance.

Abstract translation: 电阻式存储器元件与具有改进的机械稳定性和减小的寄生电容的先进节点中的逻辑元件的集成的系统和方法包括形成在底盖层和顶盖层之间延伸的公共集成层中的电阻存储元件和逻辑元件。 至少在公共积分层中形成高K值的第一金属间电介质（IMD）层，并且至少围绕电阻式存储元件，以提供高刚性和机械稳定性。 降低逻辑元件的寄生电容的低K值的第二IMD层形成在公共集成层，顶盖层上的顶层或顶盖层之间的中间层。 可以在一个或多个IMD层中形成气隙，以进一步降低电容。

公开(公告)号：US20160005749A1

公开(公告)日：2016-01-07

申请号：US14321593

申请日：2014-07-01

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Bin YANG ,  Daniel Wayne PERRY

IPC: H01L27/115 ,  H01L49/02 ,  H01L21/28

CPC classification number: H01L27/11521 ,  G11C11/223 ,  G11C16/0433 ,  H01L27/11507 ,  H01L27/1159 ,  H01L28/56 ,  H01L29/40114 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/7881

Abstract: Implementations of the technology described herein provide a Multiple Time Programmable (MTP) device, such as a Flash memory device, that implements a coupling gate in series with a floating gate. The coupling gate includes a ferroelectric capacitor and a conventional capacitor. The ferroelectric capacitor in combination with the coupling gate provides a negative capacitance such that the total capacitance of the combination of the floating gate and the coupling gate is larger than it would be if the coupling gate included only a conventional capacitor. One advantage of this device is that the effective coupling ratio between the coupling gate and the floating gate is increased. Another advantage is that the floating gate drops more voltage than conventional Multiple Time Programmable (MTP) devices.

Abstract translation: 本文描述的技术的实现提供了实现与浮动栅极串联的耦合门的多时间可编程（MTP）设备，诸如闪存设备。 耦合栅极包括铁电电容器和常规电容器。 铁电电容器与耦合栅极组合提供负电容，使得浮栅和耦合栅的组合的总电容大于如果耦合栅仅包括常规电容器的总电容。 该器件的一个优点是耦合栅极和浮置栅极之间的有效耦合比增加。 另一个优点是浮动栅极比传统的多时间可编程（MTP）器件降低了更多的电压。

公开(公告)号：US20150279479A1

公开(公告)日：2015-10-01

申请号：US14283154

申请日：2014-05-20

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Wei-Chuan CHEN ,  Seung Hyuk KANG ,  Kangho LEE

IPC: G11C17/18 ,  G11C13/00 ,  G11C17/16

CPC classification number: G11C17/18 ,  G11C11/005 ,  G11C11/5614 ,  G11C11/5685 ,  G11C11/5692 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/004 ,  G11C13/0069 ,  G11C17/165 ,  G11C2013/0042

Abstract: An anti-fuse device includes a first electrode, an insulator on the first electrode, a second electrode on the insulator, and selector logic coupled to the second electrode. The device also includes a conductive path between the first and second electrodes. The conductive path may be configured to provide a hard breakdown for one-time programmable non-volatile data storage.

Abstract translation: 反熔丝器件包括第一电极，第一电极上的绝缘体，绝缘体上的第二电极以及耦合到第二电极的选择器逻辑。 该装置还包括在第一和第二电极之间的导电路径。 导电路径可以被配置为提供一次性可编程非易失性数据存储器的硬击穿。