公开(公告)号：US20220293513A1

公开(公告)日：2022-09-15

申请号：US17198941

申请日：2021-03-11

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Bin YANG ,  Haining YANG

IPC: H01L23/522 ,  H01L21/8234 ,  H02J50/05 ,  H01L27/06 ,  H01L49/02 ,  H01L23/528

Abstract: Disclosed are examples of a device including a front side metallization portion having a front side BEOL. The device also includes a backside BEOL. The device also includes a substrate, where the substrate is disposed between the backside BEOL and the front side metallization portion. The device also includes a metal-insulator-metal (MIM) capacitor embedded in the backside BEOL.

公开(公告)号：US20220123101A1

公开(公告)日：2022-04-21

申请号：US17074026

申请日：2020-10-19

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Jun YUAN ,  Haining YANG ,  Bin YANG

IPC: H01L49/02 ,  H01L23/522

Abstract: Disclosed are examples of 3D metal-insulator-metal (MIM) capacitor structures, e.g., in semiconductor packages. The disclosed 3D MIM capacitors provide high capacitance in small areas. As such, the disclosed 3D MIM capacitors may be used as decoupling capacities for high performance computing (HPC) processors.

公开(公告)号：US20210359108A1

公开(公告)日：2021-11-18

申请号：US16875668

申请日：2020-05-15

Applicant: QUALCOMM Incorporated

Inventor： Haining YANG ,  Xia LI ,  Bin YANG

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L21/8234

Abstract: Certain aspects of the present disclosure generally relate to a semiconductor device having an insulator region disposed on at least one edge of a semiconductor fin structure. An example semiconductor device generally includes a first semiconductor region, an insulator region, a double diffusion break, and a first gate region. The first semiconductor region comprises a first fin structure and a second fin structure separated by a cavity. The insulator region is disposed along an edge of the first fin structure. The double diffusion break is disposed adjacent to the insulator region in the cavity. The first gate region is disposed around a portion of the first fin structure.

公开(公告)号：US20210304944A1

公开(公告)日：2021-09-30

申请号：US16835227

申请日：2020-03-30

Applicant: QUALCOMM Incorporated

Inventor： Kai LIU ,  Xiaoju YU ,  Xia LI ,  Bin YANG

IPC: H01F27/22 ,  H01G4/33 ,  H01G4/252 ,  H01F27/29

Abstract: Examples herein include thermally conductive pathways for glass substrates such as used by passive on glass devices that may be used to enhance the thermal conductivity of an integrated POG device. By using a thermally conductive material for passivation of the device pathways during manufacturing, the device pathways may be able to conduct heat away from the device. For example, by using a selected poly (p-phenylene benzobisoxazole) (PBO) based material (e.g., poly-p-phenylene-2, 6-benzobisoxazole) instead of conventional polyimide (PI) materials during a Cu pattern passivation process, the overall thermal performance of the device, may be enhanced.

公开(公告)号：US20210280722A1

公开(公告)日：2021-09-09

申请号：US16809534

申请日：2020-03-04

Applicant: QUALCOMM Incorporated

Inventor： Haining YANG ,  Bin YANG ,  Xia LI

IPC: H01L29/786 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/8238 ,  H01L29/66

Abstract: Strained silicon transistor, such as GAA transistors, allow for both good PMOS mobility and NMOS mobility on the same substrate. In one example, a GAA circuit may include a NMOS device on a tensile strained Si channel and a PMOS device on a compressive strained SiGe channel. In another example, a GAA circuit may include a NMOS device on a strained Si channel and a PMOS device on a relaxed SiGe channel on (110) crystalline substrate.

公开(公告)号：US20210183852A1

公开(公告)日：2021-06-17

申请号：US16712222

申请日：2019-12-12

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Haining YANG ,  Bin YANG

IPC: H01L27/06 ,  H01L29/04 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L21/8238

Abstract: Certain aspects of the present disclosure are directed to a semiconductor device. The semiconductor device generally includes a substrate, at least one silicon-on-insulator (SOI) transistor disposed above the substrate, a gate-all-around (GAA) transistor disposed above the substrate, and a fin field-effect transistor (FinFET) disposed above the substrate.

公开(公告)号：US20200328293A1

公开(公告)日：2020-10-15

申请号：US16379904

申请日：2019-04-10

Applicant: QUALCOMM Incorporated

Inventor： Gengming TAO ,  Bin YANG ,  Xia LI

IPC: H01L29/737 ,  H01L29/66 ,  H01L29/40 ,  H03F3/19

Abstract: Aspects generally relate to a heterojunction bipolar transistor (HBT), and method of manufacturing the same. The HBT including an emitter a first, a first side of a base coupled to a second side of the emitter opposite the first side of the emitter. A collector coupled to the base on a second side of the base opposite the emitter, wherein an area of a junction between the base and the collector is less than or equal to an area of a junction between the base and the emitter. A dielectric coupled to the collector. A first conductive base contact coupled to the base and adjacent to the collector and extending over a base-collector junction, the conductive base contact operative as a field plate.

公开(公告)号：US20200185384A1

公开(公告)日：2020-06-11

申请号：US16216883

申请日：2018-12-11

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Bin YANG ,  Gengming TAO

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L21/033 ,  H01L21/8238 ,  H01L29/417

Abstract: A horizontal gate-all-around (GAA) field effect transistor (FET) is described. The horizontal GAA FET includes a substrate as well as a shallow trench isolation (STI) region on the substrate. The horizontal GAA FET includes a first nano-sheet structure on the substrate and extending through the STI region. The first nano-sheet structure includes a first drain/source region stacked on a first source/drain region. The first nano-sheet structure also includes a first channel region between the first drain/source region and the first source/drain region. The horizontal GAA FET also includes a first gate on the STI region and horizontally surrounding the first channel region on four sides.

公开(公告)号：US20200111921A1

公开(公告)日：2020-04-09

申请号：US16154021

申请日：2018-10-08

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Bin YANG ,  Kai LIU

IPC: H01L29/94 ,  H01L27/13 ,  H01L49/02 ,  H01L23/532 ,  H01L29/786 ,  H01L23/00 ,  H01L23/522

Abstract: Certain aspects of the present disclosure provide a variable transistor-based capacitive element implemented on a glass or dielectric substrate. Such a variable transistor-based capacitive element may be suitable for use as a tunable capacitor in a passive-on-glass (POG) device, for example. One example device having a tunable capacitance generally includes a glass or dielectric substrate and a transistor disposed above the glass or dielectric substrate. The transistor has a gate region, a drain region, and a source region, wherein a capacitance of the transistor is configured to vary based on a voltage between the gate region and the drain region.

公开(公告)号：US20190305094A1

公开(公告)日：2019-10-03

申请号：US15937068

申请日：2018-03-27

Applicant: QUALCOMM Incorporated

Inventor： Gengming TAO ,  Bin YANG ,  Xia LI

IPC: H01L29/417 ,  H01L29/737 ,  H01L29/205 ,  H01L29/08 ,  H01L29/10 ,  H01L29/45 ,  H01L29/66 ,  H01L21/306 ,  H01L21/308 ,  H01L21/285

Abstract: In certain aspects, a heterojunction bipolar transistor (HBT) comprises a collector mesa, a base mesa on the collector mesa, and an emitter mesa on the base mesa. The base mesa has a tapered sidewall tapering from a wide bottom to a narrow top. The HBT further comprises a collector contact on a portion of the collector mesa and extending to a portion of the tapered sidewall of the base mesa.